NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 309 of 515
NXP Semiconductors
UM11029
Chapter 18: LPC84x SPI0/1
Table 335. SPI Pin Description
Function I/O Type Connect
to Use register Reference Description
SPI0_SCK I/O external
to pin any pin PINASSIGN3 Table 183 Serial Clock. SCK is a clock signal used to
synchronize the transfer of data. It is driven by the
master and received by the slave. When the SPI
interface is used, the clock is programmable to be
active-high or active-low. SCK only switches during
a data transfer. It is driven whenever the Master bit
in CFG equals 1, regardless of the state of the
Enable bit.
SPI0_MOSI I/O external
to pin any pin PINASSIGN4 Table 184 Master Out Slave In. The MOSI signal transfers
serial data from the master to the slave. When the
SPI is a master, it outputs serial data on this signal.
When the SPI is a slave, it clocks in serial data
from this signal. MOSI is driven whenever the
Master bit in SPInCfg equals 1, regardless of the
state of the Enable bit.
SPI0_MISO I/O external
to pin any pin PINASSIGN4 Table 184 Master In Slave Out. The MISO signal transfers
serial data from the slave to the master. When the
SPI is a master, serial data is input from this signal.
When the SPI is a slave, serial data is output to this
signal. MISO is driven when the SPI block is
enabled, the Master bit in CFG equals 0, and when
the slave is selected by one or more SSEL signals.
SPI0_SSEL0 I/O external
to pin any pin PINASSIGN4 Table 184 Slave Select 0. When the SPI interface is a master,
it will drive the SSEL signals to an active state
before the start of serial data and then release
them to an inactive state after the serial data has
been sent. By default, this signal is active low but
can be selected to operate as active high. When
the SPI is a slave, any SSEL in an active state
indicates that this slave is being addressed. The
SSEL pin is driven whenever the Master bit in the
CFG register equals 1, regardless of the state of
the Enable bit.
SPI0_SSEL1 I/O external
to pin any pin PINASSIGN4 Table 184 Slave Select 1.
SPI0_SSEL2 I/O external
to pin any pin PINASSIGN5 Table 185 Slave Select 2.
SPI0_SSEL3 I/O external
to pin any pin PINASSIGN5 Table 185 Slave Select 3.
SPI1_SCK I/O external
to pin any pin PINASSIGN5 Table 185 Serial Clock.
SPI1_MOSI I/O external
to pin any pin PINASSIGN5 Table 185 Master Out Slave In.
SPI1_MISO I/O external
to pin any pin PINASSIGN6 Table 186 Master In Slave Out.
SPI1_SSEL0 I/O external
to pin any pin PINASSIGN6 Table 186 Slave Select 0.
SPI1_SSEL1 I/O external
to pin any pin PINASSIGN6 Table 186 Slave Select 1.