UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
327 of 515
NXP Semiconductors
UM11029
Chapter 18: LPC84x SPI0/1
18.7.5 DMA operation
A DMA request is provided for each SPI direction, and can be used in lieu of interrupts for
transferring data by configuring the DMA controller appropriately, and enabling the Rx
and/or Tx DMA via the CFG register. The DMA controller provides an acknowledgement
signal that clears the related request when it completes handling that request.
The transmitter DMA request is asserted when Tx DMA is enabled and the transmitter can
accept more data.
The receiver DMA request is asserted when Rx DMA is enabled and received data is
available to be read.
18.7.6 Data lengths greater than 16 bits
The SPI interface handles data frame sizes from 1 to 16 bits directly. Larger sizes can be
handled by splitting data up into groups of 16 bits or less. For example, 24 bits can be
supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits, among others. Frames
of any size, including greater than 32 bits, can supported in the same way.
Details of how to handle larger data widths depend somewhat on other SPI configuration
options. For instance, if it is intended for Slave Selects to be de-asserted between frames,
then this must be suppressed when a larger frame is split into more than one part.
Sending 2 groups of 12 bits with SSEL de-asserted between 24-bit increments, for
instance, would require changing the value of the EOF bit on alternate 12-bit frames.
18.7.7 Data stalls
A stall for Master transmit data can happen in modes 0 and 2 when SCK cannot be
returned to the rest state until the MSB of the next data frame can be driven on MOSI. In
this case, the stall happens just before the final clock edge of data if the next piece of data
is not yet available.
A stall for Master receive can happen when a receiver overrun would otherwise occur if
the transmitter was not stalled. In modes 0 and 2, this occurs if the previously received
data is not read before the end of the next piece of is received. This stall happens one
clock edge earlier than the transmitter stall.
In modes 1 and 3, the same kind of receiver stall can occur, but just before the final clock
edge of the received data. Also, a transmitter stall will not happen in modes 1 and 3
because the transmitted data is complete at the point where a stall would otherwise occur,
so it is not needed.
Stalls are reflected in the STAT register by the Stalled status flag, which indicates the
current SPI status.
