NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 361 of 515
NXP Semiconductors
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Chapter 20: LPC84x Standard counter/timer (CTIMER)
20.7 Register description
The timer/counter contains the registers shown in Table 370 .
Table 370. Register overview: CTIMER (register base addresses 0x4003 8000)
Name Access Offset Description Reset
value
[1]
Section
IR R/W 0x00 Interrupt Register. The IR can be written to clear interrupts. The IR can be
read to identify which of eight possible interrupt sources are pending. 0 20.7.1
TCR R/W 0x04 Timer Control Register. The TCR is used to control the Timer Counter
functions. The Timer Counter can be disabled or reset through the TCR. 0 20.7.2
TC R/W 0x08 Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the
APB bus clock. The TC is controlled through the TCR. 0 20.7.3
PR R/W 0x0C Prescale Register. When the Prescale Counter (PC) is equal to this value,
the next clock increments the TC and clears the PC. 0 20.7.4
PC R/W 0x10 Prescale Counter. The 32 bit PC is a counter which is incremented to the
value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and controllable
through the bus interface. 0 20.7.5
MCR R/W 0x14 Match Control Register. The MCR is used to control whether an interrupt is
generated, whether the TC is reset when a Match occurs, and whether the
match register is reloaded from its shadow register when the TC is reset. 0 20.7.6
MR0 R/W 0x18 Match Register 0. MR0 can be enabled through the MCR to reset the TC,
stop both the TC and PC, and/or generate an interrupt every time MR0
matches the TC. 0 20.7.7
MR1 R/W 0x1C Match Register 1. See MR0 description. 0 20.7.7
MR2 R/W 0x20 Match Register 2. See MR0 description. 0 20.7.7
MR3 R/W 0x24 Match Register 3. See MR0 description. 0 20.7.7
CCR R/W 0x28 Capture Control Register. The CCR controls which edges of the capture
inputs are used to load the Capture Registers and whether or not an
interrupt is generated when a capture takes place. 0 20.7.8
CR0 RO 0x2C Capture Register 0. CR0 is loaded with the value of TC when there is an
event on the CAPn.0 input. 0 20.7.9
CR1 RO 0x30 Capture Register 1. See CR0 description. 0 20.7.9
CR2 RO 0x34 Capture Register 2. See CR0 description. 0 20.7.9
CR3 RO 0x38 Capture Register 3. See CR0 description. 0 20.7.9
EMR R/W 0x3C External Match Register. The EMR controls the match function and the
external match pins. 0 20.7.10
CTCR R/W 0x70 Count Control Register. The CTCR selects between Timer and Counter
mode, and in Counter mode selects the signal and edge(s) for counting. 0 20.7.11
PWMC R/W 0x74 PWM Control Register. The PWMCON enables PWM mode for the
external match pins. 0 20.7.12
MSR0 R/W 0x78 Match 0 Shadow Register. If enabled, the Match 0 Register will be
automatically reloaded with the contents of this register whenever the TC
is reset to zero. 0 20.7.13