UM11029
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User manual
Rev. 1.0 — 16 June 2017
365 of 515
NXP Semiconductors
UM11029
Chapter 20: LPC84x Standard counter/timer (CTIMER)
20.7.7 Match Registers
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
If the associated MRxRL bit in the Match Control Register is set, the Match Register will
be automatically reloaded with the current contents of its corresponding Match Shadow
register whenever the TC is cleared to zero. This transfer will take place on the same
clock edge that clocks the TC to zero.
Note: The TC is typically reset in response to an occurrence of a match on the Match
Register being used to set the cycle counter rate. A reset can also occur due to software
writing a 1 to bit 1 of the Timer Control Register.
20.7.8 Capture Control Register
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when the capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
description below, "n" represents the timer number, 0 or 1.
Note: If Counter mode is selected for a particular CAP input in the CTCR, the 3 bits for
that input in this register should be programmed as 000, but capture and/or interrupt can
be selected for the other 3 CAP inputs.
11
MR3S
Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
0 = disabled. 1 = enabled.
0
23:12
-
Reserved. Read value is undefined, only zero should be written.
-
24
MR0RL
Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero
(either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
0
25
MR1RL
Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero
(either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
0
26
MR2RL
Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero
(either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
0
27
MR3RL
Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero
(either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled.
0
31:28
-
Reserved. Read value is undefined, only zero should be written.
-
Table 376. Match Control Register (MCR, offset 0x14) bit description
Bit
Symbol
Description
Reset
Value
Table 377. Match registers (MR[0:3], offset [0x18:0x24]) bit description
Bit
Symbol
Description
Reset value
31:0
MATCH
Timer counter match value.
0
