NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 87 of 515
NXP Semiconductors
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Chapter 8: LPC84x System configuration (SYSCON)
MAINCLKPLLSEL R/W 0x048 Main clock PLL source select 0 8.6.11
MAINCLKPLLUEN R/W 0x04C Main clock PLL source update enable 0 8.6.12
MAINCLKSEL R/W 0x050 Main clock source select 0 8.6.13
MAINCLKUEN R/W 0x054 Main clock source update enable 0 8.6.14
SYSAHBCLKDIV R/W 0x058 System clock divider 1 8.6.15
- - 0x05C Reserved - -
ADCCLKSEL R/W 0x064 ADC clock source select 0 8.6.16
ADCCLKDIV R/W 0x068 ADC clock divider 0 8.6.17
SCTCLKSEL R/W 0x06C SCT clock source select 0 8.6.18
SCTCLKDIV R/W 0x070 SCT clock divider 0 8.6.19
EXTCLKSEL R/W 0x074 External clock source select 0 8.6.20
- - 0x078 Reserved - -
- - 0x07C Reserved - -
SYSAHBCLKCTRL0 R/W 0x080 System clock control 0 0x17 8.6.21
SYSAHBCLKCTRL1 R/W 0x084 System clock control 1 0x0 8.6.22
PRESETCTRL0 R/W 0x088 Peripheral reset control 0 0xFFFFFFFF 8.6.23
PRESETCTRL1 R/W 0x08C Peripheral reset control 1 0x1F 8.6.24
UART0CLKSEL R/W 0x090 Function clock source select for UART0 0x7 8.6.25
UART1CLKSEL R/W 0x094 Function clock source select for UART1 0x7 8.6.25
UART2CLKSEL R/W 0x098 Function clock source select for UART2 0x7 8.6.25
UART3CLKSEL R/W 0x09C Function clock source select for UART3 0x7 8.6.25
UART4CLKSEL R/W 0x0A0 Function clock source select for UART4 0x7 8.6.25
I2C0CLKSEL R/W 0x0A4 Function clock source select for I
2
C0 0x7 8.6.25
I2C1CLKSEL R/W 0x0A8 Function clock source select for I
2
C1 0x7 8.6.25
I2C2CLKSEL R/W 0x0AC Function clock source select for I
2
C2 0x7 8.6.25
I2C3CLKSEL R/W 0x0B0 Function clock source select for I
2
C3 0x7 8.6.25
SPI0CLKSEL R/W 0x0B4 Function clock source select for SPI0 0x7 8.6.25
SPI1CLKSEL R/W 0x0B8 Function clock source select for SPI1 0x7 8.6.25
- - 0x0BC Reserved - -
- - 0x0C0 Reserved - -
- - 0x0C4 Reserved - -
- - 0x0C8 Reserved - -
- - 0x0CC Reserved - -
FRG0DIV R/W 0x0D0 Fractional generator divider value 0x0 8.6.26
FRG0MULT R/W 0x0D4 Fractional generator multiplier value 0x0 8.6.27
FRG0CLKSEL R/W 0x0D8 FRG0 clock source select 0 8.6.28
- - 0x0DC Reserved - -
FRG1DIV R/W 0x0E0 Fractional generator divider value 0x0 8.6.29
FRG1MULT R/W 0x0E4 Fractional generator multiplier value 0x0 8.6.30
FRG1CLKSEL R/W 0x0E8 FRG1 clock source select 0 8.6.31
- - 0x0EC Reserved -
Table 125. Register overview: System configuration (base address 0x4004 8000)
…continued
Name Access Offset Description Reset value Section