NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 220 of 515
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Chapter 13: LPC84x Pin interrupts/pattern match engine
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The ORed result of all three minterms asserts the RXEV request to the CPU and the
GPIO_INT_BMAT output. That is, if any of the three minterms are true, the output is
asserted.
Related links:
Section 13.7.2
13.6 Register description
13.6.1 Pin interrupt mode register
For each of the 8 pin interrupts selected in the PINTSELn registers (see Section 8.6.42 ),
one bit in the ISEL register determines whether the interrupt is edge or level sensitive.
Table 268. Register overview: Pin interrupts and pattern match engine (base address:
0xA000 4000)
Name Access Address
offset
Description Reset
value Reference
ISEL R/W 0x000 Pin Interrupt Mode register 0 Table 269
IENR R/W 0x004 Pin interrupt level or rising edge interrupt
enable register 0 Table 270
SIENR WO 0x008 Pin interrupt level or rising edge interrupt
set register NA Table 271
CIENR WO 0x00C Pin interrupt level (rising edge interrupt)
clear register NA Table 272
IENF R/W 0x010 Pin interrupt active level or falling edge
interrupt enable register 0 Table 273
SIENF WO 0x014 Pin interrupt active level or falling edge
interrupt set register NA Table 274
CIENF WO 0x018 Pin interrupt active level or falling edge
interrupt clear register NA Table 275
RISE R/W 0x01C Pin interrupt rising edge register 0 Table 276
FALL R/W 0x020 Pin interrupt falling edge register 0 Table 277
IST R/W 0x024 Pin interrupt status register 0 Table 278
PMCTRL R/W 0x028 Pattern match interrupt control register 0 Table 279
PMSRC R/W 0x02C Pattern match interrupt bit-slice source
register 0 Table 280
PMCFG R/W 0x030 Pattern match interrupt bit slice
configuration register 0 Table 281
Table 269. Pin interrupt mode register (ISEL, address 0xA000 4000) bit description
Bit Symbol Description Reset
value Access
7:0 PMODE Selects the interrupt mode for each pin interrupt. Bit n
configures the pin interrupt selected in PINTSELn.
0 = Edge sensitive
1 = Level sensitive
0 R/W
31:8 - Reserved. - -