UM11029
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User manual
Rev. 1.0 — 16 June 2017
281 of 515
NXP Semiconductors
UM11029
Chapter 16: LPC84x DMA controller
9:8
WIDTH
Transfer width used for this DMA channel.
0
0x0
8-bit transfers are performed (8-bit source reads and destination writes).
0x1
16-bit transfers are performed (16-bit source reads and destination writes).
0x2
32-bit transfers are performed (32-bit source reads and destination writes).
0x3
Reserved setting, do not use.
11:10 -
Reserved. Read value is undefined, only zero should be written.
NA
13:12 SRCINC
Determines whether the source address is incremented for each DMA transfer.
0
0x0
No increment. The source address is not incremented for each transfer. This is the
usual case when the source is a peripheral device.
0x1
1 x width. The source address is incremented by the amount specified by Width for
each transfer. This is the usual case when the source is memory.
0x2
2 x width. The source address is incremented by 2 times the amount specified by
Width for each transfer.
0x3
4 x width. The source address is incremented by 4 times the amount specified by
Width for each transfer.
15:14 DSTINC
Determines whether the destination address is incremented for each DMA transfer. 0
0x0
No increment. The destination address is not incremented for each transfer. This is
the usual case when the destination is a peripheral device.
0x1
1 x width. The destination address is incremented by the amount specified by Width
for each transfer. This is the usual case when the destination is memory.
0x2
2 x width. The destination address is incremented by 2 times the amount specified
by Width for each transfer.
0x3
4 x width. The destination address is incremented by 4 times the amount specified
by Width for each transfer.
25:16 XFERCOUNT
Total number of transfers to be performed, minus 1 encoded. The number of bytes
transferred is: (XFE 1) x data width (as defined by the WIDTH field).
Remark:
The DMA controller uses this bit field during transfer to count down.
Hence, it cannot be used by software to read back the size of the transfer, for
instance, in an interrupt handler.
0x0 = a total of 1 transfer will be performed.
0x1 = a total of 2 transfers will be performed.
...
0x3FF = a total of 1,024 transfers will be performed.
0
31:26 -
Reserved. Read value is undefined, only zero should be written.
NA
Table 320. Transfer Configuration registers for channel 0 to 24 (XFERCFG[0:24], addresses 0x5000 8408
(XFERCFG0) to 0x5000 856C (XFERCFG24)) bit description
Bit
Symbol
Value
Description
Reset
Value