UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
91 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
8.6.5 Watchdog oscillator control register
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock can be divided to the required
output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can be
adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk = Fclkana/(2
(1 + DIVSEL)) = 9.3 kHz to 2.3 MHz (nominal values).
Remark:
Any setting of the FREQSEL bits will yield a Fclkana value within
40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the FRO or system oscillator.
Remark:
The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
Table 130. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Bit
Symbol
Value
Description
Reset
value
4:0
DIVSEL
Select divider for Fclkana.
wdt_osc_clk = Fclkana/ (2
(1 + DIVSEL))
00000: 2
(1 + DIVSEL) = 2
00001: 2
(1 + DIVSEL) = 4
to
11111: 2
(1 + DIVSEL) = 64
0
8:5
FREQSEL
Select watchdog oscillator analog output frequency
(Fclkana).
0x00
0x0
0 MHz
0x1
0.6 MHz
0x2
1.05 MHz
0x3
1.4 MHz
0x4
1.75 MHz
0x5
2.1 MHz
0x6
2.4 MHz
0x7
2.7 MHz
0x8
3.0 MHz
0x9
3.25 MHz
0xA
3.5 MHz
0xB
3.75 MHz
0xC
4.0 MHz
0xD
4.2 MHz
0xE
4.4 MHz
0xF
4.6 MHz
31:9
-
-
Reserved
0x00
