NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 106 of 515
NXP Semiconductors
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Chapter 8: LPC84x System configuration (SYSCON)
8.6.28 FRG0 clock source select register
The FRG0CLKSEL register selects the frg0_src clock, which can be the FRO, main clock,
or sys_pll.
8.6.29 Fractional generator 1 divider value register
The UART, I2C, SPI clock come from the FCLK multiplexer. The FRG1CLK is one clock
source of the FCLK multiplexer and its output from the fractional generator 1 can be
adjusted by a fractional divider:
frg1clk = frg1_src_clk/(1 + MULT / DIV)
FRG1_SRC_CLK is input clock of fractional generator 1, which can be the FRO, main
clock, or sys pll clock.
The fractional portion (1 + MULT / DIV) is determined by the two fractional divider
registers in the SYSCON block:
• The DIV value programmed in this register is the denominator of the divider used by
the fractional rate generator to create the fractional component of FRG1CLK.
•
The MULT value of the fractional divider is programmed in the FRG1MULT register.
See
Table 155 .
Remark:
To use the fractional baud rate generator, you must write 0xFF to this register to
yield a denominator value of 256. All other values are not supported.
See also:
Section 17.3.1 “Configure the USART clock and baud rate” .
Section 17.7.1 “Clocking and baud rates” .
Table 152. Fractional generator 0 multiplier value register (FRG0MULT, address 0x4004
80D4) bit description
Bit Symbol Description Reset
value
7:0 MULT Numerator of the fractional divider. MULT is equal to the
programmed value. 0
31:8 - Reserved -
Table 153. FRG0 clock source select register (FRG0CLKSEL, address 0x4004 80D8) bit
description
Bit Symbol Value Description Reset
value
1:0 SEL Clock source for FRG0_SRC clock 0x0
0x0 FRO
0x1 Main clock
0x2 SYS PLL
0x3 None
31:2 - - Reserved -