UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
297 of 515
NXP Semiconductors
UM11029
Chapter 17: LPC84x USART0/1/2/3/4
17.6.4 USART Interrupt Enable read and set register
The INTENSET register is used to enable various USART interrupt sources. Enable bits in
INTENSET are mapped in locations that correspond to the flags in the STAT register. The
complete set of interrupt enables may be read from this register. Writing ones to
implemented bits in this register causes those bits to be set. The INTENCLR register is
used to clear bits in this register.
Table 326. USART Interrupt Enable read and set register (INTENSET, address 0x4006 400C
(USART0), 0x4006 800C (USART1), 0x4006C00C (USART2), 0x4007 000C
(USART3), 0x4007 400C (USART4)) bit description
Bit
Symbol
Description
Reset
Value
0
RXRDYEN
When 1, enables an interrupt when there is a received
character available to be read from the RXDAT register.
0
1
-
Reserved. Read value is undefined, only zero should be
written.
NA
2
TXRDYEN
When 1, enables an interrupt when the TXDAT register is
available to take another character to transmit.
0
3
TXIDLEEN
When 1, enables an interrupt when the transmitter becomes
idle (TXIDLE = 1).
0
4
-
Reserved. Read value is undefined, only zero should be
written.
NA
5
DELTACTSEN
When 1, enables an interrupt when there is a change in the
state of the CTS input.
0
6
TXDISEN
When 1, enables an interrupt when the transmitter is fully
disabled as indicated by the TXDISINT flag in STAT. See
description of the TXDISINT bit for details.
0
7
-
Reserved. Read value is undefined, only zero should be
written.
NA
8
OVERRUNEN
When 1, enables an interrupt when an overrun error
occurred.
0
10:9
-
Reserved. Read value is undefined, only zero should be
written.
NA
11
DELTARXBRKEN
When 1, enables an interrupt when a change of state has
occurred in the detection of a received break condition
(break condition asserted or deasserted).
0
12
STARTEN
When 1, enables an interrupt when a received start bit has
been detected.
0
13
FRAMERREN
When 1, enables an interrupt when a framing error has been
detected.
0
14
PARITYERREN
When 1, enables an interrupt when a parity error has been
detected.
0
15
RXNOISEEN
When 1, enables an interrupt when noise is detected.
0
16
ABERREN
When 1, enables an interrupt when an autobaud error
occurs.
0
31:17 -
Reserved. Read value is undefined, only zero should be
written.
NA