UM11029
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User manual
Rev. 1.0 — 16 June 2017
344 of 515
NXP Semiconductors
UM11029
Chapter 19: LPC84x I2C0/1/2/3
19.6.4 Interrupt Enable Clear register
Writing a 1 to a bit position in INTENCLR clears the corresponding position in the
INTENSET register, disabling that interrupt. INTENCLR is a write-only register.
Bits that do not correspond to defined bits in INTENSET are reserved and only zeroes
should be written to them.
11
SLVNOTSTREN
Slave Not Stretching interrupt Enable.
0
0
The SlvNotStr interrupt is disabled.
1
The SlvNotStr interrupt is enabled.
14:12 -
Reserved. Read value is undefined, only zero
should be written.
NA
15
SLVDESELEN
Slave Deselect interrupt Enable.
0
0
The SlvDeSel interrupt is disabled.
1
The SlvDeSel interrupt is enabled.
16
MONRDYEN
Monitor data Ready interrupt Enable.
0
0
The MonRdy interrupt is disabled.
1
The MonRdy interrupt is enabled.
17
MONOVEN
Monitor Overrun interrupt Enable.
0
0
The MonOv interrupt is disabled.
1
The MonOv interrupt is enabled.
18
-
Reserved. Read value is undefined, only zero
should be written.
NA
19
MONIDLEEN
Monitor Idle interrupt Enable.
0
0
The MonIdle interrupt is disabled.
1
The MonIdle interrupt is enabled.
23:20 -
Reserved. Read value is undefined, only zero
should be written.
NA
24
EVENTTIMEOUTEN
Event time-out interrupt Enable.
0
0
The Event time-out interrupt is disabled.
1
The Event time-out interrupt is enabled.
25
SCLTIMEOUTEN
SCL time-out interrupt Enable.
0
0
The SCL time-out interrupt is disabled.
1
The SCL time-out interrupt is enabled.
31:26 -
Reserved. Read value is undefined, only zero
should be written.
NA
Table 355. Interrupt Enable Set and read register (INTENSET, address 0x4005 0008 (I2C0),
0x4005 4008 (I2C1), 0x4003 0008 (I2C2), 0x4003 4008 (I2C3)) bit description
Bit
Symbol
Value Description
Reset
value