NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 120 of 515
NXP Semiconductors
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Chapter 8: LPC84x System configuration (SYSCON)
8.7.3 System PLL functional description
The LPC84x uses the system PLL to create the clocks for the core and peripherals.
The block diagram of this PLL is shown in Figure 10 . The input frequency range is 10 MHz
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the CCO clock. The
CCO frequency range is 156 MHz to 320 MHz. This clock is divided by 2xP by the
programmable post divider to create the output clock. The output clock is then divided by
M by the programmable feedback divider to generate the feedback clock. The output
signal of the phase-frequency detector is also monitored by the lock detector, to signal
when the PLL has locked on to the input clock.
Remark:
The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 30 MHz because the main clock is limited to a
maximum frequency of 30 MHz.
8.7.3.1 Lock detector
The lock detector measures the phase difference between the rising edges of the input
and feedback clocks. Only when this difference is smaller than the so called “lock
criterion” for more than eight consecutive input clock periods, the lock output switches
from low to high. A single too large phase difference immediately resets the counter and
causes the lock signal to drop (if it was high). Requiring eight phase measurements in a
row to be below a certain figure ensures that the lock detector will not indicate lock until
both the phase and frequency of the input and feedback clocks are very well aligned. This
effectively prevents false lock indications, and thus ensures a glitch free lock signal.
Fig 10. System PLL block diagram
aaa-026632
PFD
LOCK
DETECT
LOCK
/M
analog section
pd
FCLKIN
FCCO
fro_osc_clk
sys_osc_clk
CLKIN
SYSPLLCLKSEL
2
cd
FCLKOUT /2P
pd
cd
MSEL < 4:0 >
5