NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 414 of 515
22.1 How to read this chapter
The watchdog timer is identical on all LPC84x parts.
22.2 Features
•
Internally resets chip if not reloaded during the programmable time-out period.
•
Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
•
Programmable 24-bit timer with internal fixed pre-scaler.
•
Selectable time period from 1,024 watchdog clocks (T
WDCLK

256

4) to over 67
million watchdog clocks (T
WDCLK

2
24

4) in increments of 4 watchdog clocks.
•
“Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
•
Incorrect feed sequence causes immediate watchdog event if enabled.
• The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
•
Flag to indicate Watchdog reset.
•
The Watchdog clock (WDCLK) source is the WatchDog oscillator.
• The Watchdog timer can be configured to run in Deep-sleep or Power-down mode.
•
Debug mode.
22.3 Basic configuration
The WWDT is configured through the following registers:
• Power to the register interface (WWDT PCLK clock): In the SYSAHBCLKCTRL
register, set bit 17 in
Table 146 .
•
Enable the WWDT clock source (the watchdog oscillator) in the PDRUNCFG register
(
Table 172 ). This is the clock source for the timer base.
•
For waking up from a WWDT interrupt, enable the watchdog interrupt for wake-up in
the STARTERP1 register (
Table 169 ).
UM11029
Chapter 22: LPC84x Windowed Watchdog Timer (WWDT)
Rev. 1.0 — 16 June 2017 User manual