UM11029
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User manual
Rev. 1.0 — 16 June 2017
355 of 515
NXP Semiconductors
UM11029
Chapter 19: LPC84x I2C0/1/2/3
19.7.2 Time-out
A time-out feature on an I
2
C interface can be used to detect a “stuck” bus and potentially
do something to alleviate the condition. Two different types of time-out are supported.
Both types apply whenever the I
2
C block and the time-out function are both enabled,
Master, Slave, or Monitor functions do not need to be enabled.
In the first type of time-out, reflected by the EVENTTIMEOUT flag in the STAT register, the
time between bus events governs the time-out check. These events include Start, Stop,
and all changes on the I
2
C clock (SCL). This time-out is asserted when the time between
any of these events is longer than the time configured in the TIMEOUT register. This
time-out could be useful in monitoring an I
2
C bus within a system as part of a method to
keep the bus running of problems occur.
The second type of I
2
C time-out is reflected by the SCLTIMEOUT flag in the STAT
register. This time-out is asserted when the SCL signal remains low longer than the time
configured in the TIMEOUT register. This corresponds to SMBus time-out parameter
T
TIMEOUT
. In this situation, a slave could reset its own I
2
C interface in case it is the
offending device. If all listening slaves (including masters that can be addressed as
slaves) do this, then the bus will be released unless it is a current master causing the
problem. Refer to the SMBus specification for more details.
Both types of time-out are generated when the I
2
C bus is considered busy.
19.7.3 Ten-bit addressing
Ten-bit addressing is accomplished by the I
2
C master sending a second address byte to
extend a particular range of standard 7-bit addresses. In the case of the master writing to
the slave, the I
2
C frame simply continues with data after the 2 address bytes. For the
master to read from a slave, it needs to reverse the data direction after the second
address byte. This is done by sending a Repeated Start, followed by a repeat of the same
standard 7-bit address, with a Read bit. The slave must remember that it had been
addressed by the previous write operation and stay selected for the subsequent read with
the correct partial I
2
C address.
For the Master function, the I2C is simply instructed to perform the 2-byte addressing as a
normal write operation, followed either by more write data, or by a Repeated Start with a
repeat of the first part of the 10-bit slave address and then reading in the normal fashion.
For the Slave function, the first part of the address is automatically matched in the same
fashion as 7-bit addressing. The Slave address qualifier feature (see
be used to intercept all potential 10-bit addresses (first address byte values F0 through
F6), or just one. In the case of Slave Receiver mode, data is received in the normal
Table 368. Settings for 400 KHz clock rate
Input clock to I2C
DIVVAL for CLKDIV register MSTSCLHIGH for MSTTIME
register
MSTSCLLOW for MSTTIME
register
30 MHz
14
0
1
24 MHz
14
0
0
24 MHz
11
0
1
12 MHz
5
0
1
