NXP Semiconductors LPC84x, Руководство пользователя

Страница: 121 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 121 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
8.7.3.2 Power-down control
To reduce the power consumption when the PLL clock is not needed, a PLL Power-down
mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bit to one
in the Power-down configuration register (
Table 172 ). In this mode, the internal current
reference will be turned off, the oscillator and the phase-frequency detector will be
stopped and the dividers will enter a reset state. While in PLL Power-down mode, the lock
output will be low to indicate that the PLL is not in lock. When the PLL Power-down mode
is terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal
operation and will make the lock signal high once it has regained lock on the input clock.
8.7.3.3 Divider ratio programming
8.7.3.3.1 Post divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits as shown in
Table 127 . This guarantees an
output clock with a 50% duty cycle.
8.7.3.3.2 Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one, as specified in
Table 127 .
8.7.3.3.3 Changing the divider values
Changing the divider ratio while the PLL is running is not recommended. As there is no
way to synchronize the change of the MSEL and PSEL values with the dividers, the risk
exists that the counter will read in an undefined value, which could lead to unwanted
spikes or drops in the frequency of the output clock. The recommended way of changing
between divider settings is to power down the PLL, adjust the divider settings and then let
the PLL start up again.
8.7.3.4 Frequency selection
The PLL frequency equations use the following parameters (also see Figure 10 ):
Table 174. PLL frequency parameters
Parameter System PLL
FCLKIN Frequency of sys_pllclkin (input clock to the system PLL) from the
SYSPLLCLKSEL multiplexer (see
Section 8.6.9 ).
FCCO Frequency of the Current Controlled Oscillator (CCO); 156 to 320 MHz.
FCLKOUT Frequency of sys_pllclkout. This is the PLL output frequency and must be

30 MHz.
P System PLL post divider ratio; PSEL bits in SYSPLLCTRL (see
Section 8.6.2 ).
M System PLL feedback divider register; MSEL bits in SYSPLLCTRL (see
Section 8.6.2 ).