UM11029
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
315 of 515
NXP Semiconductors
UM11029
Chapter 18: LPC84x SPI0/1
[1]
RO = Read-only, W1 = write 1 to clear.
18.6.4 SPI Interrupt Enable read and Set register
The INTENSET register is used to enable various SPI interrupt sources. Enable bits in
INTENSET are mapped in locations that correspond to the flags in the STAT register. The
complete set of interrupt enables may be read from this register. Writing ones to
implemented bits in this register causes those bits to be set. The INTENCLR register is
used to clear bits in this register. See
for details of the interrupts.
7
ENDTRANSFER End Transfer control bit. Software can set this bit to force an end to the current
transfer when the transmitter finishes any activity already in progress, as if the
EOT flag had been set prior to the last transmission. This capability is included
to support cases where it is not known when transmit data is written that it will
be the end of a transfer. The bit is cleared when the transmitter becomes idle as
the transfer comes to an end. Forcing an end of transfer in this manner causes
any specified FRAME_DELAY and TRANSFER_DELAY to be inserted.
0
RO/W1
8
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully
idle. This means that the transmit holding register is empty and the transmitter
is not in the process of sending data.
1
RO
31:9
-
Reserved. Read value is undefined, only zero should be written.
NA
NA
Table 339. SPI Status register (STAT, addresses 0x4005 8008 (SPI0), 0x4005 C008 (SPI1)) bit description
Bit
Symbol
Description
Reset
value
Access
[1]
Table 340. SPI Interrupt Enable read and Set register (INTENSET, addresses 0x4005 800C (SPI0), 0x4005 C00C
(SPI1)) bit description
Bit
Symbol
Value Description
Reset
value
0
RXRDYEN
Determines whether an interrupt occurs when receiver data is available.
0
0
No interrupt will be generated when receiver data is available.
1
An interrupt will be generated when receiver data is available in the RXDAT register.
1
TXRDYEN
Determines whether an interrupt occurs when the transmitter holding register is
available.
0
0
No interrupt will be generated when the transmitter holding register is available.
1
An interrupt will be generated when data may be written to TXDAT.
2
RXOVEN
Determines whether an interrupt occurs when a receiver overrun occurs. This happens
in slave mode when there is a need for the receiver to move newly received data to the
RXDAT register when it is already in use.
The interface prevents receiver overrun in Master mode by not allowing a new
transmission to begin when a receiver overrun would otherwise occur.
0
0
No interrupt will be generated when a receiver overrun occurs.
1
An interrupt will be generated if a receiver overrun occurs.
3
TXUREN
Determines whether an interrupt occurs when a transmitter underrun occurs. This
happens in slave mode when there is a need to transmit data when none is available.
0
0
No interrupt will be generated when the transmitter underruns.
1
An interrupt will be generated if the transmitter underruns.
