UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
473 of 515
NXP Semiconductors
UM11029
Chapter 27: LPC84x Digital-to-Analog Converter (DAC)
27.6 Operation
27.6.1 DMA counter
When the counter enable bit CNT_ENA in DACCTRL is set, a 16-bit counter will begin
counting down, at the rate selected by PCLK (see
), from the value programmed
into the DACCNTVAL register. The counter is decremented Each time the counter
reaches zero, the counter will be reloaded by the value of DACCNTVAL and the DMA
request bit INT_DMA_REQ will be set in hardware.
Note that the contents of the DACCTRL and DACCNTVAL registers are read and write
accessible, but the timer itself is not accessible for either read or write.
If the DMA_ENA bit is set in the DACCTRL register, the DAC DMA request will be routed
to the GPDMA. When the DMA_ENA bit is cleared, the default state after a reset, DAC
DMA requests are blocked.
27.6.2 Double buffering
Double-buffering is enabled only if both, the CNT_ENA and the DBLBUF_ENA bits are set
in DACCTRL. In this case, any write to the CR register will only load the pre-buffer, which
shares its register address with the CR register. The CR itself will be loaded from the
pre-buffer whenever the counter reaches zero and the DMA request is set. At the same
time the counter is reloaded with the COUNTVAL register value.
Reading the CR register will only return the contents of the CR register itself, not the
contents of the pre-buffer register.
If either the CNT_ENA or the DBLBUF_ENA bits are 0, any writes to the CR address will
go directly to the CR register.
