UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
416 of 515
NXP Semiconductors
UM11029
Chapter 22: LPC84x Windowed Watchdog Timer (WWDT)
When the Watchdog Timer is configured so that a watchdog event will cause a reset and
the counter reaches zero, the CPU will be reset, loading the stack pointer and program
counter from the vector table as for an external reset. The Watchdog time-out flag
(WDTOF) can be examined to determine if the Watchdog has caused the reset condition.
The WDTOF flag must be cleared by software.
When the Watchdog Timer is configured to generate a warning interrupt, the interrupt will
occur when the counter matches the value defined by the WARNINT register.
22.5.1 Block diagram
The block diagram of the Watchdog is shown below in the
. The synchronization
logic (PCLK - WDCLK) is not shown in the block diagram.
22.5.2 Clocking and power control
The watchdog timer block uses two clocks: PCLK and WDCLK. PCLK is used for the APB
accesses to the watchdog registers and is derived from the system clock (see
The WDCLK is used for the watchdog timer counting and is derived from the watchdog
oscillator.
Fig 52. Windowed Watchdog timer block diagram
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