UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
417 of 515
NXP Semiconductors
UM11029
Chapter 22: LPC84x Windowed Watchdog Timer (WWDT)
The synchronization logic between the two clock domains works as follows: When the
MOD and TC registers are updated by APB operations, the new value will take effect in 3
WDCLK cycles on the logic in the WDCLK clock domain.
When the watchdog timer is counting on WDCLK, the synchronization logic will first lock
the value of the counter on WDCLK and then synchronize it with PCLK, so that the CPU
can read the WDTV register.
Remark:
Because of the synchronization step, software must add a delay of three
WDCLK clock cycles between the feed sequence and the time the WDPROTECT bit is
enabled in the MOD register. The length of the delay depends on the selected watchdog
clock WDCLK.
22.5.3 Using the WWDT lock features
The WWDT supports several lock features which can be enabled to ensure that the
WWDT is running at all times:
•
Disabling the WWDT clock source
•
Changing the WWDT reload value
22.5.3.1 Disabling the WWDT clock source
If bit 5 in the WWDT MOD register is set, the WWDT clock source is locked and can not
be disabled either by software or by hardware when Sleep, Deep-sleep or Power-down
modes are entered. Therefore, the user must ensure that the watchdog oscillator for each
power mode is enabled
before
setting bit 5 in the MOD register.
In Deep power-down mode, no clock locking mechanism is in effect because no clocks
are running. However, an additional lock bit in the PMU can be set to prevent the part from
even entering Deep power-down mode (see
22.5.3.2 Changing the WWDT reload value
If bit 4 is set in the WWDT MOD register, the watchdog time-out value (TC) can be
changed only after the counter is below the value of WDWARNINT and WDWINDOW.
The reload overwrite lock mechanism can only be disabled by a reset of any type.
