UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
319 of 515
NXP Semiconductors
UM11029
Chapter 18: LPC84x SPI0/1
18.6.8 SPI Transmitter Data Register
The TXDAT register is written in order to send data via the SPI transmitter when control
information is not changing during the transfer (see
). That data will be sent
to the transmit shift register when it is available, and another character may then be
written to TXDAT.
20
EOT
End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and
remain so for at least the time specified by the Transfer_delay value in the DLY
register.
0
0
SSEL not deasserted. This piece of data is not treated as the end of a transfer.
SSEL will not be deasserted at the end of this data.
1
SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will
be deasserted at the end of this piece of data.
21
EOF
End of Frame. Between frames, a delay may be inserted, as defined by the
FRAME_DELAY value in the DLY register. The end of a frame may not be
particularly meaningful if the FRAME_DELAY value = 0. This control can be used as
part of the support for frame lengths greater than 16 bits.
0
0
Data not EOF. This piece of data transmitted is not treated as the end of a frame.
1
Data EOF. This piece of data is treated as the end of a frame, causing the
FRAME_DELAY time to be inserted before subsequent data is transmitted.
22
RXIGNORE
Receive Ignore. This allows data to be transmitted using the SPI without the need to
read unneeded data from the receiver.Setting this bit simplifies the transmit process
and can be used with the DMA.
0
0
Read received data. Received data must be read in order to allow transmission to
progress. In slave mode, an overrun error will occur if received data is not read
before new data is received.
1
Ignore received data. Received data is ignored, allowing transmission without
reading unneeded received data. No receiver flags are generated.
23
-
Reserved. Read value is undefined, only zero should be written.
NA
27:24 LEN
Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths
greater than 16 bits are supported by implementing multiple sequential transmits.
0x0 = Data transfer is 1 bit in length.
0x1 = Data transfer is 2 bits in length.
0x2 = Data transfer is 3 bits in length.
...
0xF = Data transfer is 16 bits in length.
0x0
31:28 -
Reserved. Read value is undefined, only zero should be written.
NA
Table 343. SPI Transmitter Data and Control register (TXDATCTL, addresses 0x4005 8018 (SPI0), 0x4005 C018
(SPI1)) bit description
…continued
Bit
Symbol
Value
Description
Reset
value