UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
212 of 515
NXP Semiconductors
UM11029
Chapter 12: LPC84x General Purpose I/O (GPIO)
•
The state of multiple pins in a port can be read as a byte, halfword, or word from a
PORT register.
•
The state of a selected subset of the pins in a port can be read from a Masked Port
(MPORT) register. Pins having a 1 in the port’s Mask register will read as 0 from its
MPORT register.
12.6.2 GPIO output
Each GPIO pin has an output bit in the GPIO block. These output bits are the targets of
write operations to the pins. Two conditions must be met in order for a pin’s output bit to
be driven onto the pin:
1. The pin must be selected for GPIO operation in the switch matrix (this is the default),
and
2. the pin must be selected for output by a 1 in its port’s DIR register.
If either or both of these conditions is (are) not met, writing to the pin has no effect.
There are multiple ways to change GPIO output bits:
•
Writing to a Byte Pin register loads the output bit from the least significant bit.
•
Writing to a Word Pin register loads the output bit with the OR of all of the bits written.
(This feature follows the definition of truth of a multi-bit value in programming
languages.)
•
Writing to a port’s PORT register loads the output bits of all the pins written to.
•
Writing to a port’s MPORT register loads the output bits of pins identified by zeros in
corresponding positions of the port’s MASK register.
•
Writing ones to a port’s SET register sets output bits.
•
Writing ones to a port’s CLR register clears output bits.
•
Writing ones to a port’s NOT register toggles/complements/inverts output bits.
The state of a port’s output bits can be read from its SET register. Reading any of the
registers described in
returns the state of pins, regardless of their direction
or alternate functions.
12.6.3 Masked I/O
A port’s MASK register defines which of its pins should be accessible in its MPORT
register. Zeroes in MASK enable the corresponding pins to be read from and written to
MPORT. Ones in MASK force a pin to read as 0 and its output bit to be unaffected by
writes to MPORT. When a port’s MASK register contains all zeros, its PORT and MPORT
registers operate identically for reading and writing.
Applications in which interrupts can result in Masked GPIO operation, or in task switching
among tasks that do Masked GPIO operation, must treat code that uses the Mask register
as a protected/restricted region. This can be done by interrupt disabling or by using a
semaphore.
The simpler way to protect a block of code that uses a MASK register is to disable
interrupts before setting the MASK register, and re-enable them after the last operation
that uses the MPORT or MASK register.
