NXP Semiconductors LPC84x, Руководство пользователя

Страница: 258 / 515

UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 258 of 515
NXP Semiconductors
UM11029
Chapter 15: LPC84x Reduced power modes and power management
During deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in the general purpose registers of
the PMU block.
All functional pins are tri-stated in deep power-down mode except for the WAKEUP pin
and the RESET pin.
Remark:
Setting bit 3 in the PCON register ( Table 291 ) prevents the part from entering
deep-power down mode.
15.7.7.1 Power configuration in deep power-down mode
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals are powered down. Only the WAKEUP pin, RESET pin, and the self-wake-up
timer are powered.
15.7.7.2 Programming deep power-down mode using the WAKEUP or RESET pin
The following steps must be performed to enter deep power-down mode when using the
WAKEUP pin or the RESET pin for waking up:
1. Pull the WAKEUP pin or the RESET pin externally HIGH depending on which
WAKEUP source is used.
2. Ensure that bit 3 in the PCON register ( Table 291 ) is cleared.
3. Write 0x3 to the PM bits in the PCON register (see Table 291 ).
4. Store data to be retained in the general purpose registers ( Section 15.6.2 ).
5. Write one to the SLEEPDEEP bit in the ARM Cortex-M0+ SCR register ( Table 288 ).
6. Use the ARM WFI instruction.
15.7.7.3 Wake-up from deep power-down mode using the WAKEUP pin or RESET
pin
Pulling the WAKEUP pin or RESET pin LOW wakes up the LPC84x from deep
power-down, and the part goes through the entire reset process.
1. On the WAKEUP pin or RESET pin, transition from HIGH to LOW.
–
The PMU will turn on the on-chip voltage regulator. When the core voltage reaches
the power-on-reset (POR) trip point, a system reset will be triggered and the chip
re-boots.
–
All registers except the DPDCTRL and GPREG0 to GPREG3 registers and PCON
will be in their reset state.
2. Once the chip has booted, read the deep power-down flag in the PCON register
( Table 291 ) to verify that the reset was caused by a wake-up event from deep
power-down and was not a cold reset.
3. Clear the deep power-down flag in the PCON register ( Table 291 ).
4. (Optional) Read the stored data in the general purpose registers ( Section 15.6.2 ).
5. Set up the PMU for the next deep power-down cycle.
15.7.7.4 Programming deep power-down mode using the self-wake-up timer:
The following steps must be performed to enter deep power-down mode when using the
self-wake-up timer for waking up: