NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 210 of 515
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Chapter 12: LPC84x General Purpose I/O (GPIO)
12.5.7 GPIO port set registers
Output bits can be set by writing ones to these registers, regardless of MASK registers.
Reading from these register returns the port’s output bits, regardless of pin directions.
12.5.8 GPIO port clear registers
Output bits can be cleared by writing ones to these write-only registers, regardless of
MASK registers.
12.5.9 GPIO port toggle registers
Output bits can be set by writing ones to these write-only registers, regardless of MASK
registers.
Table 261. GPIO port set register (SET[0:1], address 0xA000 2200 (SET0) to 0xA000 2204
(SET1)) bit description
Bit Symbol Description Reset
value Access
31:0 SETP Read or set output bits (bit 0 = PIOm_0,
bit 1 = PIOm_1, ..., bit 31 = PIOm_31). m = port 0 to 1;
n = pin 0 to 31 for port 0 and pin 0 to 21 for port 1.
0 = Read: output bit: write: no operation.
1 = Read: output bit; write: set output bit. 0 R/W
Table 262. GPIO port clear register (CLR[0:1], address 0xA000 2280(CLR0) to 0xA000 2284
(CLR1)) bit description
Bit Symbol Description Reset
value Access
31:0 CLRP Clear output bits (bit 0 = PIOm_0, bit 1 = PIOm_1, ...,
bit 31 = PIOm_31). m = port 0 to 1; n = pin 0 to 31 for
port 0 and pin 0 to 21 for port 1.
0 = No operation.
1 = Clear output bit. NA WO
Table 263. GPIO port toggle register (NOT[0:1], address 0xA000 2300(NOT0) to 0xA000
2304(NOT1)) bit description
Bit Symbol Description Reset
value Access
31:0 NOTP Toggle output bits (bit 0 = PIOm_0, bit 1 =PIOm_1, ..., bit 31
= PIOm_31). m = port 0 to 1; n = pin 0 to 31 for port 0 and pin
0 to 21 for port 1.
0 = no operation.
1 = Toggle output bit. NA WO