NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 94 of 515
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Chapter 8: LPC84x System configuration (SYSCON)
8.6.10 System PLL clock source update register
This register updates the clock source of the system PLL with the new input clock after the
SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.
8.6.11 Main clock PLL source select register
The MAINCLKPLLSEL register selects the main system clock, which can be the system
PLL (sys_pllclkout), or the main clock pre pll. The main system clock clocks the core, the
peripherals, and the memories.
Bit 0 of the MAINCLKUEN register (see Section 8.6.14 ) must be toggled from 0 to 1 for
the update to take effect.
8.6.12 Main clock PLL source update enable register
.The MAINCLKPLLUEN register updates the clock source of the main clock with the new
input clock after the MAINCLKPLLSEL register has been written to. In order for the update
to take effect, first write a zero to bit 0 of this register, then write a one.
Table 135. System PLL clock source update enable register (SYSPLLCLKUEN, address
0x4004 8044) bit description
Bit Symbol Value Description Reset value
0 ENA Enable system PLL clock source update 0
0 No change
1 Update clock source
31:1 - - Reserved -
Table 136. Main clock source select register (MAINCLKPLLSEL, address 0x4004 8048) bit
description
Bit Symbol Value Description Reset value
1:0 SEL Clock source for main clock 0
0x0 main_clk_pre_pll
0x1 SYS PLL
0x2 None
0x3 None
31:2 - - Reserved -
Table 137. Main clock source update enable register (MAINCLKPLLUEN, address 0x4004
804C) bit description
Bit Symbol Value Description Reset value
0 ENA Enable main clock source update. 0
0 No change
1 Update clock source
31:1 - - Reserved -