NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 438 of 515
26.1 How to read this chapter
The ADC is available on all parts. The number of available ADC channels depends on the
package type.
26.2 Features
•
12-bit successive approximation analog to digital converter.
•
Input multiplexing among 12 pins.
• Two configurable conversion sequences with independent triggers.
•
Optional automatic high/low threshold comparison and “zero crossing” detection.
•
Power-down mode and low-power operating mode.
•
Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage
level).
•
12-bit conversion rate of up to 1.2 Msamples/s.
•
Burst conversion mode for single or multiple inputs.
•
DMA support.
• Hardware calibration mode.
26.3 Basic configuration
Configure the ADC as follows:
• Use the PDRUNCFG register to power the ADC. See Table 172 . Once the ADC is
powered by the PDRUNCFG register bit, the low-power mode bit in the ADC CTRL
register can be used to turn off the ADC when it is not sampling and turn on the ADC
automatically when any of the ADC conversion triggers are raised. See
Table 443 and
Section 26.7.5 .
•
Use the SYSAHBCLKCTRL register ( Table 146 ) to enable the clock to the ADC
register interface and the ADC clock.
•
The ADC block creates four interrupts with individual entries in the NVIC. See
Table 108 .
•
The ADC analog inputs are enabled in the switch matrix block.See Table 195 .
•
The power to the ADC block is controlled by the PDRUNCFG register in the SYSCON
block. See
Table 172 .
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
Rev. 1.0 — 16 June 2017 User manual
Table 438. Pinout summary
Package ADC channels available
HVQFN33 ADC_0 to ADC_11
HVQFN48 ADC_0 to ADC_11
LQFP48 ADC_0 to ADC_11
LQFP64 ADC_0 to ADC_11