UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
372 of 515
NXP Semiconductors
UM11029
Chapter 20: LPC84x Standard counter/timer (CTIMER)
4. If a match register contains the same value as the timer reset value (the PWM cycle
length), then the PWM output will be reset to LOW on the next clock tick after the
timer reaches the match value. Therefore, the PWM output will always consist of a
one clock tick wide positive pulse with a period determined by the PWM cycle length
(i.e. the timer reload value).
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
timer goes back to zero and will stay HIGH continuously.
Note:
When the match outputs are selected to perform as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to
zero except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to one to enable the timer reset when the timer value matches the value of the
corresponding match register.
20.8.2 DMA operation
DMA requests are generated by a match of the Timer Counter (TC) register value to either
Match Register 0 (MR0) or Match Register 1 (MR1). This is not connected to the operation
of the Match outputs controlled by the EMR register. Each match sets a DMA request flag,
which is connected to the DMA controller. In order to have an effect, the DMA controller
must be configured correctly.
When a timer is initially set up to generate a DMA request, the request may already be
asserted before a match condition occurs. An initial DMA request may be avoided by
having software write a one to the interrupt flag location, as if clearing a timer interrupt.
See
. A DMA request will be cleared automatically when it is acted upon by
the DMA controller.
Note:
because timer DMA requests are generated whenever the timer value is equal to
the related Match Register value, DMA requests are always generated when the timer is
running, unless the Match Register value is higher than the upper count limit of the timer.
It is important not to select and enable timer DMA requests in the DMA block unless the
timer is correctly configured to generate valid DMA requests.
Fig 39. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and
MAT3:0 enabled as PWM outputs by the PWCON register.
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