UM11029
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User manual
Rev. 1.0 — 16 June 2017
224 of 515
NXP Semiconductors
UM11029
Chapter 13: LPC84x Pin interrupts/pattern match engine
13.6.9 Pin interrupt falling edge register
This register contains ones for pin interrupts selected in the PINTSELn registers (see
) on which a falling edge has been detected. Writing ones to this register
clears falling edge detection. Ones in this register assert an interrupt request for pins that
are enabled for falling-edge interrupts. All edges are detected for all pins selected by the
PINTSELn registers, regardless of whether they are interrupt-enabled.
13.6.10 Pin interrupt status register
Reading this register returns ones for pin interrupts that are currently requesting an
interrupt. For pins identified as edge-sensitive in the Interrupt Select register, writing ones
to this register clears both rising- and falling-edge detection for the pin. For level-sensitive
pins, writing ones inverts the corresponding bit in the Active level register, thus switching
the active level on the pin.
13.6.11 Pattern Match Interrupt Control Register
The pattern match control register contains one bit to select pattern-match interrupt
generation (as opposed to pin interrupts which share the same interrupt request lines),
and another to enable the RXEV output to the CPU. This register also allows the current
state of any pattern matches to be read.
If the pattern match feature is not used (either for interrupt generation or for RXEV
assertion) bits SEL_PMATCH and ENA_RXEV of this register should be left at 0 to
conserve power.
Table 277. Pin interrupt falling edge register (FALL, address 0xA000 4020) bit description
Bit
Symbol Description
Reset
value
Access
7:0
FDET
Falling edge detect. Bit n detects the falling edge of the pin
selected in PINTSELn.
Read 0: No falling edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a falling edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear falling edge detection for this pin.
0
R/W
31:8
-
Reserved.
-
-
Table 278. Pin interrupt status register (IST, address 0xA000 4024) bit description
Bit
Symbol Description
Reset
value
Access
7:0
PSTAT
Pin interrupt status. Bit n returns the status, clears the edge
interrupt, or inverts the active level of the pin selected in
PINTSELn.
Read 0: interrupt is not being requested for this interrupt pin.
Write 0: no operation.
Read 1: interrupt is being requested for this interrupt pin.
Write 1 (edge-sensitive): clear rising- and falling-edge
detection for this pin.
Write 1 (level-sensitive): switch the active level for this pin (in
the IENF register).
0
R/W
31:8
-
Reserved.
-
-
