UM11029
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User manual
Rev. 1.0 — 16 June 2017
346 of 515
NXP Semiconductors
UM11029
Chapter 19: LPC84x I2C0/1/2/3
2. SCLTIMEOUT checks only the time that the SCL signal remains low while the bus is
not idle. The SCLTIMEOUT status flag in the STAT register is set if SCL remains low
longer than the time configured in the TIMEOUT register. The SCLTIMEOUT status
flag can cause an interrupt if enabled to do so by the SCLTIMEOUTEN bit in the
INTENSET register. The SCLTIMEOUT can be used with the SMBus.
.
19.6.6 Clock Divider register
The CLKDIV register divides down the Peripheral Clock (PCLK) to produce the I
2
C
function clock that is used to time various aspects of the I
2
C interface. The I
2
C function
clock is used for some internal operations in the I
2
C block and to generate the timing
required by the I
2
C bus specification, some of which are user configured in the MSTTIME
register for Master operation and the SLVTIME register for Slave operation.
See
Section 19.7.1.1 “Rate calculations”
for details on bus rate setup.
Table 357. Time-out value register (TIMEOUT, address 0x4005 0010 (I2C0), 0x4005 4010
(I2C1), 0x4003 0010 (I2C2), 0x4003 4010 (I2C3)) bit description
Bit
Symbol
Description
Reset
value
3:0
TOMIN
Time-out time value, bottom four bits. These are hard-wired to 0xF.
This gives a minimum time-out of 16 I
2
C function clocks and also a
time-out resolution of 16 I
2
C function clocks.
0xF
15:4
TO
Time-out time value. Specifies the time-out interval value in increments
of 16 I
2
C function clocks, as defined by the CLKDIV register. To change
this value while I
2
C is in operation, disable all time-outs, write a new
value to TIMEOUT, then re-enable time-outs.
0x000 = A time-out will occur after 16 counts of the I
2
C function clock.
0x001 = A time-out will occur after 32 counts of the I
2
C function clock.
...
0xFFF = A time-out will occur after 65,536 counts of the I
2
C function
clock.
0xFFF
31:16 -
Reserved. Read value is undefined, only zero should be written.
NA
Table 358. I
2
C Clock Divider register (CLKDIV, address 0x4005 0014 (I2C0), 0x4005 4014
(I2C1), 0x4003 0014 (I2C2), 0x4003 4014 (I2C3)) bit description
Bit
Symbol
Description
Reset
value
15:0
DIVVAL This field controls how the clock (PCLK) is used by the I
2
C functions
that need an internal clock in order to operate.
0x0000 = PCLK is used directly by the I
2
C function.
0x0001 = PCLK is divided by 2 before use by the I
2
C function.
0x0002 = PCLK is divided by 3 before use by the I
2
C function.
...
0xFFFF = PCLK is divided by 65,536 before use by the I
2
C function.
0
31:16 -
Reserved. Read value is undefined, only zero should be written.
NA
