NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 80 of 515
NXP Semiconductors
UM11029
Chapter 8: LPC84x System configuration (SYSCON)
1. By default, the FRO is enabled. If required, the FRO can be enabled in the
PDRUNCFG register:
Section 8.6.47 “Power configuration register”
2. Select the fro_oscout (30 MHz/24 MHz/18 MHz) using the set_fro_frequency API call:
Chapter 9 “LPC84x FRO API ROM routine” and Figure 9 “UM11029 clock generation
(continued)” .
3. The FROOSCCTRL register can be used to select direct fro_oscout or divided
fro_oscout for fro clock.
4. Use the FRODIRECTCLKUEN register to update the fro clock:
Section 8.6.7 “FRO direct clock source update register”
5. Based on the Low Power boot bit in the FAIM, default divide by 2 is replaced with
divide by 16.
8.3.2 Set up the PLL
The PLL creates a stable output clock at a higher frequency than the input clock. If you
need a main clock with a frequency higher than the input clock, use the PLL to boost the
input frequency.
1. Power up the system PLL in the PDRUNCFG register.
Section 8.6.47 “Power configuration register”
2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input
options:
–
FRO: 12 MHz internal oscillator (default).
–
External clock input: It can be external crystal oscillator using the
XTALIN/XTALOUT pins or CLKIN from external pin.
Remark:
The min frequency for PLL is 10 MHz.
Section 8.6.9 “System PLL clock source select register”
3. Update the PLL clock source in the SYSPLLCLKUEN register.
Section 8.6.10 “System PLL clock source update register”
4. Configure the PLL M and N dividers.
Section 8.6.2 “System PLL control register”
5. Wait for the PLL to lock by monitoring the PLL lock status.
Section 8.6.3 “System PLL status register”
8.3.3 Configure the main clock and system clock
The clock source for the registers and memories is derived from main clock. The main
clock can be sourced from the main clock pre PLL or from the PLL.
The divided main clock is called the system clock and clocks the core, the memories, and
the peripherals (register interfaces and peripheral clocks).
1. Select the main clock pre PLL. You have the following options:
–
FRO: 12 MHz internal oscillator (default).