UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
246 of 515
NXP Semiconductors
UM11029
Chapter 15: LPC84x Reduced power modes and power management
15.4 Pin description
In deep power-down the WAKEUP pin PIO0_4, RESET pin PIO0_5, and the self-wake-up
timer clock input WKTCLKIN on pin PIO0_28 are functional (if enabled). The WAKEUP
and the RESET functions can be disabled in the DPDCTRL register to lower the power
consumption even more. In this case, enable the self-wake-up timer to provide an internal
wake-up signal. See
Section 15.6.3 “Deep power-down control register”
Remark:
When entering deep power-down mode, an external pull-up resistor is required
on the WAKEUP pin or the RESET pin to hold it HIGH.
Table 288. System control register (SCR, address 0xE000 ED10) bit description
Bit
Symbol
Description
Reset
value
0
-
Reserved.
0
1
SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to
Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR to
Thread mode.
Setting this bit to 1 enables an interrupt driven application to
avoid returning to an empty main application.
0
2
SLEEPDEEP
Controls whether the processor uses sleep or deep-sleep as
its low power mode:
0 = sleep
1 = deep sleep.
0
3
-
Reserved.
0
4
SEVONPEND
Send Event on Pending bit:
0 = only enabled interrupts or events can wake-up the
processor, disabled interrupts are excluded
1 = enabled events and all interrupts, including disabled
interrupts, can wake up the processor.
When an event or interrupt enters pending state, the event
signal wakes up the processor from WFE. If the processor is
not waiting for an event, the event is registered and affects
the next WFE.
The processor also wakes up on execution of an
SEV
instruction.
0
31:5
-
Reserved.
0
