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Chapter 16: LPC84x DMA controller
can range from a single transfer to many transfers. A transfer that is started by a trigger
can still be paced using the channel’s DMA request. This allows sending a string to a
serial peripheral, for instance, without overrunning the peripheral’s transmit buffer.
Each trigger input to the DMA has a corresponding output that can be used as a trigger
input to another channel. The trigger outputs appear in the trigger source list for each
channel and can be selected through the DMA_INMUX registers as inputs to other
channels.
16.5.2 DMA Modes
The DMA controller doesn’t really have separate operating modes, but there are ways of
using the DMA controller that have commonly used terminology in the industry.
Once the DMA controller is set up for operation, using any specific DMA channel requires
initializing the registers associated with that channel (see
Table 295 ), and supplying at
least the channel descriptor, which is located somewhere in memory, typically in on-chip
SRAM (see
Section 16.6.3 ). The channel descriptor is shown in Table 296 .
The source and destination end addresses, as well as the link to the next descriptor are
just memory addresses that can point to any valid address on the device. The starting
address for both source and destination data is the specified end address minus the
transfer length (XFERCOUNT * the address increment as defined by SRCINC and
DSTINC). The link to the next descriptor is used only if it is a linked transfer.
After the channel has had a sufficient number of DMA requests and/or triggers, depending
on its configuration, the initial descriptor will be exhausted. At that point, if the transfer
configuration directs it, the channel descriptor will be reloaded with data from memory
pointed to by the “Link to next descriptor” entry of the initial channel descriptor.
Descriptors loaded in this manner look slightly different the channel descriptor, as shown
in
Table 297 . The difference is that a new transfer configuration is specified in the reload
descriptor instead of being written to the XFERCFG register for that channel.
This process repeats as each descriptor is exhausted as long as reload is selected in the
transfer configuration for each new descriptor.
Table 296. Channel descriptor
Offset Description
+ 0x0 Reserved
+ 0x4 Source data end address
+ 0x8 Destination end address
+ 0xC Link to next descriptor
Table 297. Reload descriptors
Offset Description
+ 0x0 Transfer configuration.