UM11029
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© NXP Semiconductors N.V. 2017. All rights reserved.
User manual
Rev. 1.0 — 16 June 2017
466 of 515
NXP Semiconductors
UM11029
Chapter 26: LPC84x 12-bit Analog-to-Digital Converter (ADC)
state (as designated by the TRIGPOL bit). If this condition is not met, a trigger will be
generated immediately upon enabling the sequence - even though no actual transition
has occurred on the trigger input.
26.7.3 Software-triggered conversion
There are two ways that software can trigger a conversion sequence:
1. Start Bit: The first way to software-trigger an sequence is by setting the START bit in
the corresponding SEQn_CTRL register. The response to this is identical to
occurrence of a hardware trigger on that sequence. Specifically, one cycle of
conversions through that conversion sequence will be immediately triggered except
as indicated above.
2. Burst Mode: The other way to initiate conversions is to set the BURST bit in the
SEQn_CTRL register. As long as this bit is 1 the designated conversion sequence will
be continuously and repetitively cycled through. Any new software or hardware trigger
on this sequence will be ignored.
If a bursting A sequence is allowed to be interrupted (i.e. the LOWPRIO bit in its
SEQA_CTRL register is set to 1 and a software or hardware trigger for the B sequence
occurs, then the burst will be immediately interrupted and a B sequence will be initiated.
The interrupted A sequence will resume continuous cycling, starting with the aborted
conversion, after the alternate sequence has completed.
26.7.4 Interrupts
There are four interrupts that can be generated by the ADC:
•
Conversion-Complete or Sequence-Complete interrupts for sequences A and B
•
Threshold-Compare Out-of-Range Interrupt
•
Data Overrun Interrupt
Any of these interrupt requests may be individually enabled or disabled in the INTEN
register.
26.7.4.1 Conversion-Complete or Sequence-Complete interrupts
For each of the two sequences, an interrupt request can either be asserted at the end of
each A/D conversion performed as part of that sequence or when the entire sequence of
conversions is completed. The MODE bits in the SEQn_CTRL registers select between
these alternative behaviors.
If the MODE bit for a sequence is 0 (conversion-complete mode) then the interrupt flag for
that sequence will reflect the state of the DATAVALID bit in the global data register
(SEQn_GDAT) for that sequence. In this case, reading the SEQn_GDAT register will
automatically clear the interrupt request.
If the MODE bit for the sequence is 1 (sequence-complete mode) then the interrupt flag
must be written-to by software to clear it (except when used as a DMA trigger, in which
case it will be cleared in hardware by the DMA engine).
