NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 122 of 515
NXP Semiconductors
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Chapter 8: LPC84x System configuration (SYSCON)
8.7.3.4.1 Normal mode
In this mode the PLL is enabled, giving a 50% duty cycle clock with the following
frequency relations:
(1)
To select the appropriate values for M and P, it is recommended to follow these steps:
1. Specify the input clock frequency Fclkin.
2. Calculate M to obtain the desired output frequency Fclkout with M = F
clkout
/ F
clkin
.
3. Find a value so that FCCO = 2

P

F
clkout
.
4. Verify that all frequencies and divider values conform to the limits specified in
Table 127 .
Remark:
The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is

30 MHz.
Table 175 shows how to configure the PLL for a 12 MHz crystal oscillator using the
SYSPLLCTRL register ( Table 127 ).
8.7.3.4.2 PLL Power-down mode
In this mode, the internal current reference will be turned off, the oscillator and the
phase-frequency detector will be stopped and the dividers will enter a reset state. While in
PLL Power-down mode, the lock output will be low, to indicate that the PLL is not in lock.
When the PLL Power-down mode is terminated by SYSPLL_PD bit to zero in the
Power-down configuration register (
Table 172 ), the PLL will resume its normal operation
and will make the lock signal high once it has regained lock on the input clock.
Fclkout M Fclkin

FCCO
 
2 P
   
= =
Table 175. PLL configuration examples
FCLKIN
frequency FCLKOUT
frequency MSEL bits
Table 127
M divider
value PSEL bits
Table 127
P divider
value FCCO
frequency System
clock
12 MHz 24 MHz 00001
(binary) 2 10 (binary) 4 192 MHz 24 MHz