NXP Semiconductors LPC84x, Руководство пользователя

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UM11029 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
User manual Rev. 1.0 — 16 June 2017 245 of 515
15.1 How to read this chapter
The LPC84x provides an on-chip API in the boot ROM to optimize power consumption in
active and sleep modes. See
Section 16.1 .
Read this chapter to configure the reduced power modes deep-sleep mode, power-down
mode, and deep power-down mode.
15.2 Features
• Reduced power modes control
•
Low-power oscillator control
•
Five general purpose backup registers to retain data in deep power-down mode
15.3 Basic configuration
The PMU is always on as long as V
DD
is present.
If using the WAKEUP or RESET function, disable the hysteresis for the WAKEUP pad or
RESET pad in the DPDCTRL register when the supply voltage VDD is below 2.2 V. See
Table 293 .
If using the WKTCLKIN function, disable the hysteresis for that pin in the DPDCTRL
register. See
Table 293 .
15.3.1 Low power modes in the ARM Cortex-M0+ core
Entering and exiting the low power modes is always controlled by the ARM Cortex-M0+
core. The SCR register is the software interface for controlling the core’s actions when
entering a low power mode. The SCR register is located on the ARM private peripheral
bus. For details, see
Ref. 3 .
15.3.1.1 System control register
The System control register (SCR) controls entry to and exit from a low power state. This
register is located on the private peripheral bus and is a R/W register with reset value of
0x0000 0000. The SCR register allows to put the ARM core into sleep mode or the entire
system in deep-sleep or power-down mode. To set the low power state with
SLEEPDEEP = 1 to either deep-sleep or power-down or to enter the deep power-down
mode, use the PCON register (
Table 291 ).
UM11029
Chapter 15: LPC84x Reduced power modes and power
management
Rev. 1.0 — 16 June 2017 User manual