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ADwin-Gold

Hardware Manual

Version 2.3 November 2002

Summary of Contents for ADwin-Gold

Page 1: ...ADwin Gold Hardware Manual Version 2 3 November 2002...

Page 2: ...2 ADwin Gold Hardware Manual Version 2 3 ADwin...

Page 3: ...rdware 23 6 3 Initializing the Software 24 6 4 Adjustment 25 6 5 Processes for Calibration 26 7 DA Add on 28 8 OPT Add on 29 8 1 Digital Inputs 30 8 2 Digital Outputs 30 9 CO1 Counter Add On 32 9 1 Ha...

Page 4: ...without any errors advice for efficient operation Information stands for further information in this documentation or for other sources such as manuals data sheets literature etc File names and file...

Page 5: ...rks appropriately The manufacturer of the systems described in this documentation takes into account that the person who uses the systems is a specialist A specialist is a person who due to his educat...

Page 6: ...ating system for the DSP of the ADwin system has been optimized to reach the fastest response times possible It manages parallel processes in a multitasking manner Low priority processes are managed b...

Page 7: ...esponse to an instruction coming from the PC Thus embedding the ADwin system into various programming languages and standard software packages for measurements is easily made because they have only to...

Page 8: ...e very fast with the 16 bit ADCs highly accurately The standard version of the ADwin Gold system is equipped with two optio nal eight analog outputs with an output voltage range of 10 to 10 Volt and a...

Page 9: ...d in combination with an ADpcmcia link adapter ADpcmcia link adapter for connection to a notebook with ADlink cable Gold USB Set external USB adapter with connecting cables Gold ENET Set interface for...

Page 10: ...ents by ordering on request the ADlink cable shielded on one end only Please make sure that the shielding is not reduced for instance by taking measures for bleeding off interferences such as connecti...

Page 11: ...avorable circumstances cause damages to other equipments the input resistance at the analog inputs will get into the status of low impedance so that damages may occur at the ADwin Gold system and othe...

Page 12: ...m permissible current For fast and easy programming there are standard instructions available in the compiler ADbasic which enable a user to easily measure or output data see also ADbasic manual Use o...

Page 13: ...s power supply by using the power connector of the link adapter For using the system with an external power supply unit you need the subminia ture connector described above of the series 712 with the...

Page 14: ...difference between positive and negative input inner and outer conducter of the BNC socket is measured The system has 16 analog inputs IN1 IN16 with male BNC sockets which are arranged in 2 rows The i...

Page 15: ...ive voltage and 65 535 digits correspond to the maximum positive voltage The value for 65 536 digits exactly 10 Volt is just outside the measurement range so that you will get a maximum voltage value...

Page 16: ...uations can be used for both ADC types Conversion Digit Voltage For the DACs For the ADCs 12 bit and 16 bit Tolerance Ranges Slight variations regarding the calculated values may be within the toleran...

Page 17: ...d remove the bottom part Pull of very carefully and softly the attached printed circuit board off the main printed circuit board After replugging the jumper s put the printed circuit board s again bac...

Page 18: ...as digital outputs see pin assignment below Only in this configuration will you be able to totally access the inputs and outputs wit the instructions DIGIN DIGIN_WORD DIGOUT_WORD SET_DIGOUT CLEAR_DIG...

Page 19: ...by using the individual instructions If you apply these instructions skilfully you may be able to execute faster measurements It is important to set the START_CONV instruction in a sufficient time de...

Page 20: ...1 e t i b 6 1 2 C D A s u t a t s C O E e t i b 2 1 1 C D A s u t a t s C O E e t i b 2 1 2 C D A s u t a t s C O E e 0 3 0 0 0 4 0 2 t i b 6 1 1 C D A r e t s i g e r t u o d a e r x x x x x x x x x...

Page 21: ...x x x x x x x x x x x 0 0 2 0 0 4 0 2 n o i s r e v n o c t r a t s d n a r e t s i g e r e h t o t e t i r w 1 C A D y l e t a i d e m m i x x x x x x x x x x x 0 1 2 0 0 4 0 2 n o i s r e v n o c t...

Page 22: ...n i d a e r e u l a v l a t i g i d x 0 B 1 0 0 4 0 2 1 3 O I D o t 6 1 O I D s r e t s i g e r t u p n I x x x x x x x x x x x 0 C 1 0 0 4 0 2 5 1 O I D o t 0 0 O I D s r e t s i g e r t u p t u O x...

Page 23: ...mperature of the device of approx 20 to 25 degrees Celsius room temperature the system reaches the operating temperature approx 30 minutes after power up Calibration is only possible when the device i...

Page 24: ...n value in FPAR_1 for 16 bit ADC PAR_2 mean value in FPAR_2 for 12 bit ADC Please pay attention to the fact that the set channel corresponds to the con nected measurement cables during the following a...

Page 25: ...e digital value for the test value max is displayed 2 Set the voltage for the test value min at the input Check again the converted digital value PAR_1 and adjust it with the offset trimmer 3 Check as...

Page 26: ...channel number 0 not allowed IF PAR_9 0 then PAR_9 32768 64080 9 555664V at a voltage range of 10V 32768 0V 1456 9 555664V EVENT DAC PAR_10 PAR_9 output value 2 Read voltage with the 16 bit ADC Proce...

Page 27: ...on August 08 2000 Usage of the variables PAR_2 value which has been read 0 65 535 PAR_3 channel number 1 16 FPAR_1 mean value INIT GLOBALDELAY 20000 IF PAR_3 0 then PAR_3 1 prevent channel number 0 no...

Page 28: ...on of the trimmers can be seen in the following picture Connectors Programming and calibration CONN 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 DAC 8 DAC 7 DAC 6 DAC 5 GND DAC...

Page 29: ...V 24V 12V 5V 24V 12V 5V 24V 12V 5V 24V 12V 5V 24V 12V 5V EVENT DIO 15 DIO 14 DIO 13 DIO 12 DIO 11 DIO 10 DIO 08 DIO 09 DIO 07 DIO 06 DIO 05 DIO 04 DIO 03 DIO 02 DIO 01 DIO 00 DIO 16 DIO 17 DIO 18 DIO...

Page 30: ...at least 7 mA in order to light up the LED in the optocoupler 8 2 Digital Outputs After you have connected an external voltage be tween 5 and 30 Volt to VCC Pin 12 CONN 2 and OPT GND Pin 13 CONN 2 the...

Page 31: ...L 2 3 V VH I h g i H 0 2 I D E L VN I 2 4V 3 5 A m s t u p t u o r o t s i s n a r T r e b m u N 6 1 n o i t a l o s I D N G h C 0 0 5 V e g a t l o v r o t c e l l o c t x E V C C 5 0 3 t n e r r u...

Page 32: ...ng direction 0 count down 1 count up Four edge evaluation Every edge of the signals phase shifted by 90 degrees at A CLK and B DIR causes the counter to increment decrement The counting direction is d...

Page 33: ...n u o C 4 3 2 1 s t n e m m o C t i B 3 2 1 0 R A E L C _ T N C 0 0 0 0 t c e f f e o n 1 1 1 1 r e t n u o c r a e l c E L B A N E _ T N C 0 0 0 0 r e t n u o c e l b a s i d 1 1 1 1 o o t s r e t n...

Page 34: ...lues which are interpreted by ADbasic as numerical values according to the model of the circle below The most significant bit MSB is interpreted as a sign the highest posi tive number 231 1 follows th...

Page 35: ...the last counter value which has been read out is not registered Such a lap overflow occurs after some 3 minutes with an input frequency of 20 MHz or after more than 14 minutes with 5 MHz You will fi...

Page 36: ...ncy of 20 MHz The direction is derived from a high signal count up or low signal count down at the DIR input direction This signal can be static for a fixed count direction or dynamic for changing dir...

Page 37: ...durations shorter than 100 ns are not inc remented Changing the phase shift will have an effect on the maximum input frequency If it differs from 90 degrees the maximum input frequency of 5 MHz decrea...

Page 38: ...ion measurements In this mode the counter values are latched into latch A at every positive edge and the previous data are overwritten The pulse width will be derived from the counter value difference...

Page 39: ...e Initialize disable counter clear counter mode internal reference clock at internal CLK input of the counter with 20 MHz or with 5 MHz set input CLR LATCH to LATCH mode enable counter read out latch...

Page 40: ...x 0 3 3 0 0 4 0 2 H C T A L r o R L C t u p n I x x x x t u p n i R L C 0 x t u p n i H C T A L 1 x 0 4 3 0 0 4 0 2 e s l u p r o r e t n u o c t n e v e e s l u p m I t n e m e r u s a e m n o i t a...

Page 41: ...equipped with an OPT add on then the inputs of the CO1 add on have also opto couplers The notes given in the chapter 8 OPT add on apply also for the CO1 add on Depending on the counter mode the maximu...

Page 42: ...again As memory a Flash EPROM with the size of 512 kByte is used With the installation of the ADwin Developer Software from the supplied ADwin CD ROM the utility programs for the bootloader are automa...

Page 43: ...ower supply unit is rated for the highest load and maximum expansions of the ADwin Gold For larger distances ADlink cables with 5 m can be provided All ADlink cables can also be delivered with a shiel...

Page 44: ...o d d a A D d l o G 5 2 s n o d d a r e h t o d l o G 5 1 n o i t a r e p O e r u t a r e p m e t s i s s a h c T e s a c 0 0 6 C y t i d i m u h e v i t a l e r F l e r n o i t a s n e d n o c o n 0...

Page 45: ...i b 2 1 C D A e m i t n o i s r e v n o c t v n o c 8 0 s e g n a r t n e m e r u s a e m r o t c a f n i a g k Un i 1 k 0 1 7 1 1 5 9 9 9 V 2 k 5 9 5 5 7 9 9 4 4 k 5 2 9 7 7 8 9 4 2 8 k 5 2 1 9 3 9...

Page 46: ...2 P S D A r o s s e c o r P s r e t e m a r a P l o b m y S s n o i t i d n o C n i m p y t x a m t i n U U P C e p y t C R A H S 2 6 0 1 2 P S D A r e r u t c a f u n a m s e c i v e D g o l a n A y...

Page 47: ...x d e t r e v n o c 0 6 0 0 0 4 0 2 2 C A D r e t s i g e r o t n i e t i r w y l n o x x x x x x x x x x x 0 7 0 0 0 4 0 2 3 C A D r e t s i g e r o t n i e t i r w y l n o x x x x x x x x x x x 0 8...

Page 48: ...e t i r w 3 C A D y l e t a i d e m m i x x x x x x x x x x x e b o t e u l a v l a t i g i d x d e t r e v n o c 4 2 2 0 0 4 0 2 3 r e t n u o c A h c t a l t u o d a e r x x x x x x x x x x x x h c...

Page 49: ...conversion EMC Electromagnetic compatibility ESD Electrostatic discharge FPGA Field programmable gate array FSR Full scale range GND Ground h Hex Hexadecimal number trailing I O Input Output IC Integr...

Page 50: ...ure 7 2 Position of the potentiometers for calibration DA add on 28 Figure 8 1 Pin assignment of the OPT add on 29 Figure 8 2 Position of the jumpers for the input voltage range OPT add on 29 A 5 List...

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