NXP Semiconductors LPC84x, Руководство пользователя

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User manual Rev. 1.0 — 16 June 2017 311 of 515
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Chapter 18: LPC84x SPI0/1
18.6.1 SPI Configuration register
The CFG register contains information for the general configuration of the SPI. Typically,
this information is not changed during operation. Some configurations, such as CPOL,
CPHA, and LSBF should not be made while the SPI is not fully idle. See the description of
the master idle status (MSTIDLE in
Table 339 ) for more information.
Remark:
If the interface is re-configured from Master mode to Slave mode or the reverse
(an unusual case), the SPI should be disabled and re-enabled with the new configuration.
INTENSET R/W 0x00C SPI Interrupt Enable read and Set. A
complete value may be read from this
register. Writing a 1 to any
implemented bit position causes that
bit to be set. 0 Table 340
INTENCLR W 0x010 SPI Interrupt Enable Clear. Writing a 1
to any implemented bit position causes
the corresponding bit in INTENSET to
be cleared. NA Table 341
RXDAT R 0x014 SPI Receive Data NA Table 342
TXDATCTL R/W 0x018 SPI Transmit Data with Control 0 Table 343
TXDAT R/W 0x01C SPI Transmit Data 0 Table 344
TXCTL R/W 0x020 SPI Transmit Control 0 Table 345
DIV R/W 0x024 SPI clock Divider 0 Table 346
INTSTAT R 0x028 SPI Interrupt Status 0x02 Table 347
Table 336. Register overview: SPI (base address 0x4005 8000 (SPI0) and 0x4005 C000 (SPI1))
…continued
Name Access Offset Description Reset
value Reference
Table 337. SPI Configuration register (CFG, addresses 0x4005 8000 (SPI0), 0x4005 C000 (SPI1)) bit
description
Bit Symbol Value Description Reset
value
0 ENABLE SPI enable. 0
0 Disabled. The SPI is disabled and the internal state machine and counters are reset.
1 Enabled. The SPI is enabled for operation.
1 - Reserved. Read value is undefined, only zero should be written. NA
2 MASTER Master mode select. 0
0 Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are
inputs, MISO is an output.
1 Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals
are outputs, MISO is an input.
3 LSBF LSB First mode enable. 0
0 Standard. Data is transmitted and received in standard MSB first order.
1 Reverse. Data is transmitted and received in reverse order (LSB first).