MAX32600 User’s Guide
System Configuration and Management
4.1 Power Ecosystem and Operating Modes
4.1.3.1
Low Power Mode 2 (LP2: Peripheral Management Unit)
The
Peripheral Management Unit (PMU)
is a DMA engine for the
MAX32600
. It enables the lowest noise floor for analog measurements and reduced operating
power for peripherals. The PMU acts like an internal state machine that can orchestrate events via programmable
for:
• Peripheral to Memory
• Memory to Peripheral
• Analog to Memory
• Memory to Analog
–
Synchronization of analog measurements
–
Control and synchronization of pulse train signals and events
During this state, the ARM Cortex-M3 has relinquished control to the PMU. The ARM Cortex-M3 is in sleep mode, resulting in power reduction and noise minimization.
To further reduce power consumption and noise, only the required clocks and data buses are active during LP2: PMU. Typically, the
MAX32600
draws 1.2mA of
current (24MHz clock) with a single channel of the PMU active. Each additional channel draws approximately 100uA of current.
4.1.3.2
Low Power Mode 3 (LP3: RUN)
LP3: RUN mode is under full firmware control using the ARM core. During this state, the ARM Cortex-M3 and the digital core are fully powered and awake. The
clocks to each peripheral are gated dynamically and only clock the circuitry in use. Firmware executes from the internal flash memory based on the instruction cache.
Typical power of 175uA/MHz is achieved in LP3: RUN. This is the default power up state.
Reference
for detailed information regarding entering LP3: RUN from an initial boot up.
4.1.4
Power State Matrix Control Options
The
depicts the four major power states and how control is handled in the
MAX32600
.
The
illustrates:
• Hardware controlled powering of circuit blocks
• Firmware controllable power options
• Firmware controllable clock gating
Note
The chip hardware will power the minimal amount of circuitry necessary to achieve functionality of each mode. To achieve the lowest optimized
power solution, the user must fully analyze the usage case and choose the appropriate power and clock gating options.
Rev.1.3 April 2015
Maxim Integrated
Page 35
Содержание MAX32600
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