Maxim Integrated MAX32600, Руководство пользователя

Страница: 532 / 687

MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock
Active low reset for PLL
CLKMAN_CLK_CONFIG.pll_input_select
Field Bits Default Access Description
pll_input_select 14 no effect R/W PLL Input Select
Selects input clock source for PLL
• 0: Selects HFX output as PLL input clock source
• 1: Selects 24MHz RO output as PLL input clock src
CLKMAN_CLK_CONFIG.pll_divisor_select
Field Bits Default Access Description
pll_divisor_select 17:16 no effect R/W PLL Divisor Select
Must be set to match the PLL input frequency, to allow the intended 48MHz output frequency to be generated.
• 00b: PLL input frequency is 24MHz
• 01b: PLL input frequency is 12MHz
• 1xb: PLL input frequency is 8MHz
CLKMAN_CLK_CONFIG.pll_8mhz_enable
Field Bits Default Access Description
pll_8mhz_enable 18 no effect R/W PLL 8MHz Enable
Rev.1.3 April 2015 Maxim Integrated Page 514