MAX32600 User’s Guide
Communication Peripherals
7.1 I²C
I2CS0_INTFL.rx_fifo_empty
Field
Bits
Default
Access
Description
rx_fifo_empty
3
0
W1C
Rx FIFO Empty Interrupt Status
Write 1 to clear.
Set to 1 by hardware when the Rx FIFO is empty.
I2CS0_INTFL.rx_fifo_2q_full
Field
Bits
Default
Access
Description
rx_fifo_2q_full
4
0
W1C
Rx FIFO 2Q Full Interrupt Status
Write 1 to clear.
Set to 1 by hardware when the Rx FIFO is half full (two quarters).
I2CS0_INTFL.rx_fifo_3q_full
Field
Bits
Default
Access
Description
rx_fifo_3q_full
5
0
W1C
Rx FIFO 3Q Full Interrupt Status
Write 1 to clear.
Set to 1 by hardware when the Rx FIFO is three-quarters full.
I2CS0_INTFL.rx_fifo_full
Field
Bits
Default
Access
Description
rx_fifo_full
6
0
W1C
Rx FIFO Full Interrupt Status
Rev.1.3 April 2015
Maxim Integrated
Page 247
Содержание MAX32600
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