Maxim Integrated MAX32600, Руководство пользователя

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MAX32600 User’s Guide Communication Peripherals 7.3 UART
Default Access Description
n/a R/W FIFO Read Space for Results Data
Reads from this space pull data from the SPI Master Results FIFO. This read space supports single accesses as well as burst accesses; access widths of 8-bit,
16-bit and 32-bit are supported. Writes to this space are ignored.
The SPI Master Results FIFO is 8 bits wide and 32 levels deep. Reading an 8-bit value from this space results in a single pull from the read end of the FIFO. Reading
a 16-bit value results in two byte pulls (b0 and b1) from the read end of the FIFO; the resulting 16-bit return value is b1:b0 where b1 is the MSB and b0 is the LSB.
Reading a 32-bit value results in four byte pulls (b0, b1, b2, b3) from the read end of the FIFO; the resulting 32-bit return value is b3:b2:b1:b0 where b3 is the MSB
and b0 is the LSB.
7.3 UART
7.3.1 Overview
The MAX32600 provides two UART ports which can be used to communicate with external devices requiring an asynchronous serial protocol. Features of the
MAX32600 UARTs:
• Flexible baud rate generation based on the module clock frequency (equal to the system clock source or a subdivide of the system clock source)
• Programmable word size (5- to 8-bits), stop bits, and parity settings
• Automatic parity and framing error detection
• Automatic flow control can be enabled for RTS and CTS lines
• 8-byte FIFO in both directions (separate read/RX and write/TX FIFOs)
• Interrupts available for frame error, parity error, CTS, RX FIFO overrun, and FIFO full/partially full conditions
7.3.2 UART Port and Pin Configurations
UART Wiring Configuration
• RX, TX, CTS, RTS
Note See Pin Layout for a detailed mapping of MAX32600 multiplexed function locations. Functional priority distinction is included in the mapping.
Rev.1.3 April 2015 Maxim Integrated Page 283