Maxim Integrated MAX32600, Руководство пользователя

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MAX32600 User’s Guide Peripheral Management Unit (PMU) 6.4 Registers (PMU)
RD SIZE WR SIZE Operation
00b 10b Perform 8-bit reads and pack data into 32-bit writes
01b 00b Perform 16-bit reads and unpack into 8-bit writes
01b 01b Perform 16-bit reads and writes
01b 10b Perform 16-bit reads and pack data into 32-bit writes
10b 00b Perform 32-bit reads and unpack data into 8-bit writes
10b 01b Perform 32-bit reads and unpack data into 16-bit writes
10b 10b Perform 32-bit reads and writes
XX 11 (Reserved)
11b XX (Reserved)
RD INC
• Setting this bit to 0 disables auto-incrementing of the read address. This may be useful when reading from FIFO storage elements.
WR INC
• Setting this bit to 1 enables auto-incrementing of the write address. This may be useful when writing to SRAM memory.
LENGTH
• Length of total transfer (in bytes) from read address to write address.
BURST
• Maximum burst length of transfer (in bytes) from read address to write address when specified interrupt source is detected.
6.4 Registers (PMU)
6.4.1 Module PMU Registers
Rev.1.3 April 2015 Maxim Integrated Page 208