Maxim Integrated MAX32600, Руководство пользователя

Страница: 523 / 687

MAX32600 User’s Guide System Clock, Timers/Counters, Watchdog Timers and Real Time Clock 10.1 System Clock
Firmware Control of the External 32kHz Clock
The 32kHz RTC clock is enabled with the PWRSEQ_REG0.pwr_rtcen_run bit for LP2: PMU and LP3: RUN and PWRSEQ_REG0.pwr_rtcen_slp bit for LP0: STOP
and LP1: STANDBY .
10.1.3.4 Phase Lock Loop
An on-chip Phase Lock Loop (PLL) is provided to allow for generation of a 48MHz USB clock using lower value external quartz crystals or ceramic resonators. The
crystal clock multiplier is controlled via the
CLKMAN_CLK_CONFIG register. Note that proper divisor select is required with the different frequencies of the XTAL
reference clocks.
The PLL is selectable between 2X, 4X, and 6X frequency multiplication modes and has a nominal output frequency of 48MHz. Note that the maximum frequency the
CPU can be operated at is 24MHz. The PLL’s 48MHz output is divided down by two in order to be used as a CPU clock source. To select the multiplier for the PLL,
set the
CLKMAN_CLK_CONFIG.pll_divisor_select bit field appropriately.
PLL Frequency Divisor Selection
PLL Divisor Select PLL Multiplier Input Clock Freq (HFXIN / Internal Osc)
00b 2X 24MHz
01b 4X 12MHz
1xb 6X 8MHz
Rev.1.3 April 2015 Maxim Integrated Page 505