MAX32600 User’s Guide
Introduction
2.5 Memory
Fetches between the instruction cache and the flash memory go through the code descrambler, so that the content stored in the instruction cache has already been
descrambled.
Code access to the internal data SRAM is not cached; instruction fetches from SRAM are always performed directly. Data fetches (D-Code, as opposed to I-Code
fetches for the purposes of decoding instructions) are also not cached and are performed directly. This includes fetches of local constant literals that are used by
certain ARM instruction op codes.
Firmware has the option to flush the instruction cache manually at any point using a control register. When code mapped into a cached instruction space is updated
(for example, if an in-application programming modification is made to an executable area of program flash), the cache should be flushed to ensure that the latest
version of the code will be accessible and that stale cache contents will not be used instead of the new flash programmed values.
2.5.3
Internal Data SRAM
The internal data SRAM on the
MAX32600
ranges from 16 KB to 32 KB in size and has a 32-bit internal width. It is mapped into the SRAM bit-banding access
region beginning at address 0x2000_0000, and so it can be read/written either a full 32-bit word at a time, or a single bit at a time using the bit-band alias region
(beginning at 0x2200_0000). The bit-banding function can only be used when the data SRAM is being accessed by the ARM core itself, since the ARM core handles
the remapping from the bit-banding alias area to a read-modify-write sequence (or single read/mask/shift for a bit read function) of the standard memory area.
The data SRAM can be read or written freely by the application, and can be used for either code or data access. The contents of the data SRAM are not battery-
backed. The data SRAM is also used to hold the stack.
The
MAX32600
supports multiple SRAM memory sizes within the maximum allowed address space of 32 KB. When a smaller size than the maximum is used (such
as 16 KB) attempts to access out-of-range addresses within the 32 KB maximum range will generate an AHB bus error. The effect of this error condition will be
determined by the AHB master accessing the bus; for example, the ARM core will respond to this error condition by generating a MemFault system exception. Other
bus masters (e.g., the DMA AHB bus master or the JTAG/PTP bus master) may respond differently or ignore the AHB error altogether; the exact results of this
condition are determined by the designer of the AHB master interface block.
2.5.4
Peripheral Management Unit (PMU)
The PMU controller on the
MAX32600
provides a generalized, flexible mechanism to perform automatic read and/or write sequences to peripherals and areas of
internal SRAM memory. The PMU controller includes multiple channels which can be connected to different peripherals or memory areas and is capable of operation
during sleep mode.
Peripherals which can be read from or written to using PMU channels (accessing AHB mapped memory areas) include:
• The ADC
• Any of the four DAC instances
• Any of the UART instances
• Any of the SPI instances
Rev.1.3 April 2015
Maxim Integrated
Page 14
Содержание MAX32600
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