Maxim Integrated MAX32600, Руководство пользователя

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MAX32600 User’s Guide Analog Front End 8.3 ADC
8.3.3 ADC Operation
The control registers for the ADC can be accessed directly by the CPU to setup, begin, and retrieve the results of ADC conversion operations. For higher performance,
it is often required (depending on the application) to put the CPU into the lower power mode
Low Power Mode 2 (LP2: Peripheral Management Unit) to reduce overall
clock noise to achieve the highest possible accuracy of the measured signal.
When performing ADC operations with the CPU in LP2: PMU, the Peripheral Management Unit (PMU) can be used to monitor the progress of ADC conversion
sequences, set up conditions for different portions of an analog conversion operation, transfer resulting sample data from the ADC output FIFO to the main system
RAM, and many other functions. Since the PMU is capable of operating independently while the Cortex-M3 CPU is in Sleep mode, it is possible to perform a wide
variety of complex analog tasks without needing to wake up the CPU during the process. See
Power Ecosystem and Operating Modes for further information.
Figure 8.6: ADC Block Diagram
Rev.1.3 April 2015 Maxim Integrated Page 405