MAX32600 User’s Guide
Peripheral Management Unit (PMU)
6.2 PMU Operation
6.2
PMU Operation
The PMU is a six-channel, programmable state machine that executes user-created op codes and operands that reside in the
MAX32600
memory space. Acting
as an AHB master, the PMU can access any memory address in either the AHB or APB memory space. Each channel runs independently and shares accesses to
the AHB/APB address space using an internal round-robin arbiter, on an op code-by-op code basis, with priority encoding. Priority ranges from channel one with
the highest priority and channel six with the lowest priority. The PMU runs from a fixed-source clock and is clocked at the same frequency as the main
MAX32600
system clock (scaling configured by
), which has a maximum frequency of 24MHz.
PMU op codes and operands are executed sequentially, with the user specifying the address of the first op code for each enabled channel. Op code execution for
a given PMU channel is terminated when an op code has been executed with the STOP bit set or an error condition has been encountered. There is no limit to the
number of op codes that can be executed.
Each PMU channel has two control registers that control the operation of the channel. The op code address register (
) is used to set the 32-bit
starting address of the first op code. The channel configuration register (
) is used to start and stop the execution of op codes and operands for that
channel. This register also reports status and error information.
6.2.1
PMU Channel Setup
To begin execution on a PMU channel, the user must specify an area of memory, which may be RAM or Flash memory, to hold the PMU op codes and operands.
Once the PMU op codes and operands are written to memory, the user must set the starting address of the first op code using the
register, followed
by setting the START bit in the
register. The PMU op code engine will then fetch the first op code and associated operands and begin processing. Upon
completion of the first PMU op code, subsequent op codes are fetched sequentially from memory unless otherwise specified by a
, or
op
code or an op code with the STOP bit set.
Completion of the entire series of PMU op codes will be signified by clearing of the START bit in the
register, and if programmed to do so, an interrupt
to the CPU may be asserted. Each PMU channel operates independently in this manner.
6.2.2
PMU Channel Arbitration
The PMU is an AHB bus master, and allows each of the channels access to the AHB/APB memory space. Arbitration between PMU channels for access to the bus
master is performed by a round-robin scheduler, on an op code-by-op code basis, with priority encoding.
For example: If three PMU channels are active, execution would start with channel 1, op code 1 then proceed to channel 2, op code 1; channel 3, op code 1; channel
1, op code 2; etc. If a channel’s op code is blocked due to flow control, execution of the next active channel’s op code will subsequently occur. The WAIT, POLL, and
TRANSFER op codes do not block the round-robin arbitration.
Rev.1.3 April 2015
Maxim Integrated
Page 195
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