Functional Peripherals Description
82
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Peripherals
part of a dynamic clock management control loop.
The timer consists of three registers. See
for bits description of the SYSTICK registers:
•
SysTick Control and Status Register (STCSR): A control and status register to configure its clock,
enable the counter, enable the SysTick interrupt, and determine counter status.
•
SysTick Reload Value Register (STRVR): The reload value for the counter, used to provide the
counter's wrap value.
•
SysTick Current Value Register (STCVR): The current value of the counter.
When enabled, the timer counts down on each clock from the reload value to zero, reloads (wraps) to the
value in the STRVR register on the next clock edge, then decrements on subsequent clocks. Clearing the
STRVR register disables the counter on the next wrap. When the counter reaches zero, the COUNT
status bit is set. The COUNT bit clears on reads.
Writing to the STCVR register clears the register and the COUNT status bit. The write does not trigger the
SysTick exception logic. On a read, the current value is the value of the register at the time the register is
accessed.
The SysTick counter reload and current value are undefined at reset; the correct initialization sequence for
the SysTick counter is:
1. Program the value in the STRVR register.
2. Clear the STCVR register by writing to it with any value.
3. Configure the STCSR register for the required operation.
NOTE:
When the processor is halted for debugging, the counter does not decrement.
The timer is clocked with respect to a reference clock. The reference clock in MSP432P4xx
devices is same as the CPU free running clock (FCLK). There is no support for an external
clock to be used as SysTICK reference clock. Consequently, the CLKSOURCE bit in the
SYSTICK Control and Status register must always be written as 1 (to indicate CPU clock as
reference clock).
2.2.2 Nested Vectored Interrupt Controller (NVIC)
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. (See
for bit description of NVIC registers).
The NVIC supports:
•
64 interrupts.
•
A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority,
so level 0 is the highest interrupt priority.
•
Low-latency exception and interrupt handling.
•
Level and pulse detection of interrupt signals.
•
Dynamic re-prioritization of interrupts.
•
Grouping of priority values into group priority and subpriority fields.
•
Interrupt tail-chaining.
•
An external Non-maskable interrupt (NMI).
The processor automatically stacks its state on exception entry and unstacks this state on exception exit,
with no instruction overhead, providing low latency exception handling.
