Texas Instruments SimpleLink MSP432P4 Series, Technical Reference Manual

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Instruction Set Summary
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76 SLAU356I – March 2015 – Revised June 2019
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Cortex-M4F Processor
Table 1-12. Cortex-M4F Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
LDREXB Rt, [Rn] Load Register Exclusive with Byte –
LDREXH Rt, [Rn] Load Register Exclusive with Halfword –
LDRH, LDRHT Rt, [Rn, #offset] Load Register with Halfword –
LDRSB, LDRSBT Rt, [Rn, #offset] Load Register with Signed Byte –
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with Signed Halfword –
LDRT Rt, [Rn, #offset] Load Register with word –
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left N, Z, C
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right N, Z, C
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result –
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result –
MOV, MOVS Rd, Op2 Move N, Z, C
MOVT Rd, #imm16 Move Top –
MOVW, MOV Rd, #imm16 Move 16-bit constant N, Z, C
MRS Rd, spec_reg Move from Special Register to general register –
MSR spec_reg, Rm Move from general register to Special Register N, Z, C, V
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N,Z
MVN, MVNS Rd, Op2 Move NOT N, Z, C
NOP – No Operation –
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N, Z, C
ORR, ORRS {Rd,} Rn, Op2 Logical OR N, Z, C
PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword –
POP reglist Pop registers from stack –
PUSH reglist Push registers onto stack –
QADD {Rd,} Rn, Rm Saturating double and Add Q
QADD16 {Rd,} Rn, Rm Saturating Add 16 –
QADD8 {Rd,} Rn, Rm Saturating Add 8 –
QASX {Rd,} Rn, Rm Saturating Add and Subtract with Exchange –
QDADD {Rd,} Rn, Rm Saturating Add Q
QDSUB {Rd,} Rn, Rm Saturating double and Subtract Q
QSAX {Rd,} Rn, Rm Saturating Subtract and Add with Exchange –
QSUB {Rd,} Rn, Rm Saturating Subtract Q
QSUB16 {Rd,} Rn, Rm Saturating Subtract 16 –
QSUB8 {Rd,} Rn, Rm Saturating Subtract 8 –
RBIT Rd, Rn Reverse Bits –
REV Rd, Rn Reverse byte order in a word –
REV16 Rd, Rn Reverse byte order in each halfword –
REVSH Rd, Rn Reverse byte order in bottom halfword and sign extend –
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right N, Z, C
RRX, RRXS Rd, Rm Rotate Right with Extend N, Z, C
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract N, Z, C, V
SADD16 {Rd,} Rn, Rm Signed Add 16 GE
SADD8 {Rd,} Rn, Rm Signed Add 8 GE
SASX {Rd,} Rn, Rm Signed Add and Subtract with Exchange GE
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry N, Z, C, V
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract –
SDIV {Rd,} Rn, Rm Signed Divide –
SEL {Rd,} Rn, Rm Select bytes –