Texas Instruments SimpleLink MSP432P4 Series, Technical Reference Manual

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Instruction Set Summary
77 SLAU356I – March 2015 – Revised June 2019
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Cortex-M4F Processor
Table 1-12. Cortex-M4F Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
SEV – Send Event –
SHADD16 {Rd,} Rn, Rm Signed Halving Add 16 –
SHADD8 {Rd,} Rn, Rm Signed Halving Add 8 –
SHASX {Rd,} Rn, Rm Signed Halving Add and Subtract with Exchange –
SHSAX {Rd,} Rn, Rm Signed Halving Subtract and Add with Exchange –
SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16 –
SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8 –
SMLABB, SMLABT,
SMLATB, SMLATT
Rd, Rn, Rm, Ra Signed Multiply Accumulate Long (halfwords) Q
SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q
SMLAL RdLo, RdHi, Rn, Rm
Signed Multiply with Accumulate (32 x 32 + 64), 64-bit
result
–
SMLALBB, SMLALBT,
SMLALTB, SMLALTT
RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long, halfwords –
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual –
SMLAWB, SMLAWT Rd, Rn, Rm, Ra Signed Multiply Accumulate, word by halfword Q
SMLSD Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q
SMLSLD RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual
SMMLA Rd, Rn, Rm, Ra Signed Most significant word Multiply Accumulate –
SMMLS, SMMLR Rd, Rn, Rm, Ra Signed Most significant word Multiply Subtract –
SMMUL, SMMULR {Rd,} Rn, Rm Signed Most significant word Multiply –
SMUAD {Rd,} Rn, Rm Signed dual Multiply Add Q
SMULBB, SMULBT
SMULTB, SMULTT
{Rd,} Rn, Rm Signed Multiply (halfwords) –
SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result –
SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword –
SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract –
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q
SSAT16 Rd, #n, Rm Signed Saturate 16 Q
SSAX {Rd,} Rn, Rm Signed Subtract and Add with Exchange GE
SSUB16 {Rd,} Rn, Rm Signed Subtract 16 –
SSUB8 {Rd,} Rn, Rm Signed Subtract 8 –
STM Rn{!}, reglist Store Multiple registers, increment after –
STMDB, STMEA Rn{!}, reglist Store Multiple registers, decrement before –
STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after –
STR Rt, [Rn, #offset] Store Register word –
STRB, STRBT Rt, [Rn, #offset] Store Register byte –
STRD Rt, Rt2, [Rn, #offset] Store Register two words –
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive –
STREXB Rd, Rt, [Rn] Store Register Exclusive Byte –
STREXH Rd, Rt, [Rn] Store Register Exclusive Halfword –
STRH, STRHT Rt, [Rn, #offset] Store Register Halfword –
STRT Rt, [Rn, #offset] Store Register word –
SUB, SUBS {Rd,} Rn, Op2 Subtract N, Z, C, V
SUB, SUBW {Rd,} Rn, #imm12 Subtract –
SVC #imm Supervisor Call –
SXTAB {Rd,} Rn, Rm,{,ROR #} Extend 8 bits to 32 and add –
SXTAB16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add –
SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add –