Memory Model
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SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Processor
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Some memory accesses are buffered or speculative.
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describes the cases where the memory system ensures the order of memory accesses.
Otherwise, if the order of memory accesses is critical, software must include memory barrier
instructions to force that ordering. The Cortex-M4F has the following memory barrier instructions:
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The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete
before subsequent memory transactions.
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The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions
complete before subsequent instructions execute.
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The Instruction Synchronization Barrier (ISB) instruction ensures that the effect of all completed
memory transactions is recognizable by subsequent instructions.
Memory barrier instructions can be used in the following situations:
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MPU programming
If the MPU settings are changed and the change must be effective on the very next instruction, use a
DSB instruction to ensure the effect of the MPU takes place immediately at the end of context
switching.
Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the
MPU region or regions, if the MPU configuration code was accessed using a branch or call. If the MPU
configuration code is entered using exception mechanisms, then an ISB instruction is not required.
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Vector table
If the program changes an entry in the vector table and then enables the corresponding exception, use
a DMB instruction between the operations. The DMB instruction ensures that if the exception is taken
immediately after being enabled, the processor uses the new exception vector.
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Self-modifying code
If a program contains self-modifying code, use an ISB instruction immediately after the code
modification in the program. The ISB instruction ensures subsequent instruction execution uses the
updated program.
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Memory map switching
If the system contains a memory map switching mechanism, use a DSB instruction after switching the
memory map in the program. The DSB instruction ensures subsequent instruction execution uses the
updated memory map.
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Dynamic exception priority change
When an exception priority has to change when the exception is pending or active, use DSB
instructions after the change. The change then takes effect on completion of the DSB instruction.
Memory accesses to Strongly Ordered memory, such as the System Control Block, do not require the use
of DMB instructions.
For more information on the memory barrier instructions, see the Cortex-M4 instruction set chapter in the
Cortex-M4 Devices Generic User Guide
1.4.5 Bit-Banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-
band regions occupy the lowest 1MB of the SRAM and peripheral memory regions. Accesses to the 32MB
SRAM alias region map to the 1MB SRAM bit-band region, as shown in
. Accesses to the 32MB
peripheral alias region map to the 1MB peripheral bit-band region, as shown in
.
NOTE:
A word access to the SRAM or the peripheral bit-band alias region maps to a single bit in
the SRAM or peripheral bit-band region.
A word access to a bit band address results in a word access to the underlying memory, and similarly for
halfword and byte accesses. This allows bit band accesses to match the access requirements of the
underlying peripheral.
