Debug Peripherals Description
91
SLAU356I – March 2015 – Revised June 2019
Copyright © 2015–2019, Texas Instruments Incorporated
Cortex-M4F Peripherals
When the FPU is not in flush-to-zero mode, operations are performed on subnormal operands. If the
operation does not produce a tiny result, it returns the computed result, and the UFC flag, FPSCR[3], is
not set. The IXC flag, FPSCR[4], is set if the operation is inexact. If the operation produces a tiny result,
the result is a subnormal or zero value, and the UFC flag, FPSCR[3], is set if the result was also inexact.
2.2.5.6
Exceptions
The FPU sets the cumulative exception status flag in the FPSCR register as required for each instruction,
in accordance with the FPv4 architecture. The FPU does not support user-mode traps. The exception
enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also has six output pins,
FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the status of one of the cumulative
exception flags. All these outputs are ORed and given on a single interrupt line in MSP432Pxx devices.
The processor can reduce the exception latency by using lazy stacking. See the Auxiliary Control Register
(ACTLR). This means that the processor reserves space on the stack for the FP state, but does not save
that state information to the stack. See the Armv7-M Architecture Reference Manual (available from Arm)
for more information.
2.2.5.7
Enabling the FPU
The FPU is disabled from reset. You must enable it before you can use any floating-point instructions.
In many compilers, such as in TI's Code Composer Studio IDE, if the hardware FPU option is selected in
the compiler setting, the initialization code enables the FPU before entering the main() function. In this
case, users do not need to manually turn on the FPU in the main application code.
The processor must be in privileged mode to read from and write to the Coprocessor Access Control
(CPAC) register. The following example code sequence enables the FPU in both privileged and user
modes.
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]; wait for store to complete
DSB
;reset pipeline now the FPU is enabled
ISB
2.3
Debug Peripherals Description
MSP432P4xx debug subsystem comprises the following components.
2.3.1 FPB
Flash Patch and Breakpoint unit supports six instruction comparators and two literal comparators for
breakpoint. Code patching through FPB is supported in MSP432P4xx devices only when the device
security features (JTAG and SWD lock or IP protection) are not enabled. When device security is enabled,
any attempt to patch using FPB generates an internal reset to the system.
2.3.2 DWT
Data Watchpoint and Trace Unit containing four watchpoint units. It can be used for the following:
•
A hardware watchpoint
•
A PC sampler event trigger
•
A data address sampler event trigger.
The DWT contains counters for:
•
Clock cycles (CYCCNT)
